From 30aa72020d7be30e64e526074e65bb055f6c9a35 Mon Sep 17 00:00:00 2001
From: Pisit Sawangvonganan <pisit@ndrsolution.com>
Date: Sat, 18 Jan 2025 22:16:59 +0700
Subject: [PATCH] dts: arm: nxp: s32: add `#address-cells` to interrupt
 provider

Add `#address-cells = <0>;` to interrupt provider nodes in
the NXP S32 device tree to resolve warnings: e.g.
Warning (interrupt_provider): /soc/interrupt-controller@47800000: Missing
Warning (interrupt_provider): /soc/siul2@40520000/eirq0@40520010: Missing

This ensures compliance with device tree specifications and
eliminates build warnings.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
---
 dts/arm/nxp/nxp_s32k344_m7.dtsi  | 1 +
 dts/arm/nxp/nxp_s32z27x_r52.dtsi | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/dts/arm/nxp/nxp_s32k344_m7.dtsi b/dts/arm/nxp/nxp_s32k344_m7.dtsi
index 0020324b2a2..4a473213210 100644
--- a/dts/arm/nxp/nxp_s32k344_m7.dtsi
+++ b/dts/arm/nxp/nxp_s32k344_m7.dtsi
@@ -90,6 +90,7 @@
 			eirq0: eirq@40290010 {
 				compatible = "nxp,s32-siul2-eirq";
 				reg = <0x40290010 0xb4>;
+				#address-cells = <0>;
 				interrupts = <53 0>, <54 0>, <55 0>, <56 0>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
index 578dffddb77..974ee633e15 100644
--- a/dts/arm/nxp/nxp_s32z27x_r52.dtsi
+++ b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
@@ -105,6 +105,7 @@
 			compatible = "arm,gic-v3", "arm,gic";
 			reg = <0x47800000 0x10000>,
 				<0x47900000 0x80000>;
+			#address-cells = <0>;
 			interrupt-controller;
 			#interrupt-cells = <4>;
 			status = "okay";
@@ -219,6 +220,7 @@
 			eirq0: eirq0@40520010 {
 				compatible = "nxp,s32-siul2-eirq";
 				reg = <0x40520010 0xb4>;
+				#address-cells = <0>;
 				interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
@@ -270,6 +272,7 @@
 			eirq1: eirq1@40d20010 {
 				compatible = "nxp,s32-siul2-eirq";
 				reg = <0x40d20010 0xb4>;
+				#address-cells = <0>;
 				interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
@@ -345,6 +348,7 @@
 			eirq4: eirq4@42520010 {
 				compatible = "nxp,s32-siul2-eirq";
 				reg = <0x42520010 0xb4>;
+				#address-cells = <0>;
 				interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
@@ -418,6 +422,7 @@
 			eirq5: eirq5@42d20010 {
 				compatible = "nxp,s32-siul2-eirq";
 				reg = <0x42d20010 0xb4>;
+				#address-cells = <0>;
 				interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
 				interrupt-controller;
 				#interrupt-cells = <2>;