debug: coredump: add xtensa intel adsp, support toolchains
Adds compatibility with Intel ADSP GDB from Zephyr SDK and from Cadence toolchain to coredump_gdbserver.py. Adds CAVS 15-25 (APL) register definitions. Implements handle_register_single_read_packet to serve ADSP GDB p packets. Prevents BSA from changing between stack dump printout and coredump by taking lock. Observed to be necessary for accurate results on slower simulated platforms. Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
This commit is contained in:
Lauren Murphy
Anas Nashif
parent
b034711f59
commit
318e6db239
8 changed files with 249 additions and 59 deletions
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@ -9,12 +9,13 @@
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#include <xtensa-asm2.h>
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#define ARCH_HDR_VER 1
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#define XTENSA_BLOCK_HDR_VER 1
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#define XTENSA_BLOCK_HDR_VER 2
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enum xtensa_soc_code {
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XTENSA_SOC_UNKNOWN = 0,
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XTENSA_SOC_SAMPLE_CONTROLLER,
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XTENSA_SOC_ESP32,
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XTENSA_SOC_INTEL_ADSP,
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};
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struct xtensa_arch_block {
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@ -28,14 +29,16 @@ struct xtensa_arch_block {
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*/
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uint8_t soc;
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/* Future versions of Xtensa coredump
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* may expand minimum set of registers
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/* Future versions of Xtensa coredump may expand
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* minimum set of registers
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*
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* (This should stay the second field for the same
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* reason as the first once we have more versions)
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*/
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uint16_t version;
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uint8_t toolchain;
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struct {
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/* Minimum set shown by GDB 'info registers',
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* skipping user-defined register EXPSTATE
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@ -101,13 +104,18 @@ void arch_coredump_info_dump(const z_arch_esf_t *esf)
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arch_blk.version = XTENSA_BLOCK_HDR_VER;
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#if CONFIG_SOC_XTENSA_SAMPLE_CONTROLLER
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arch_blk.soc = XTENSA_SOC_SAMPLE_CONTROLLER;
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#elif CONFIG_SOC_ESP32
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arch_blk.soc = XTENSA_SOC_ESP32;
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#else
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arch_blk.soc = XTENSA_SOC_UNKNOWN;
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#endif
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#if CONFIG_SOC_XTENSA_SAMPLE_CONTROLLER
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arch_blk.soc = XTENSA_SOC_SAMPLE_CONTROLLER;
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#elif CONFIG_SOC_ESP32
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arch_blk.soc = XTENSA_SOC_ESP32;
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#elif CONFIG_SOC_FAMILY_INTEL_ADSP
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arch_blk.soc = XTENSA_SOC_INTEL_ADSP;
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#else
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arch_blk.soc = XTENSA_SOC_UNKNOWN;
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#endif
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/* Set in top-level CMakeLists.txt for use with Xtensa coredump */
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arch_blk.toolchain = XTENSA_TOOLCHAIN_VARIANT;
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__asm__ volatile("rsr.exccause %0" : "=r"(arch_blk.r.exccause));
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@ -14,6 +14,7 @@
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#include <xtensa_backtrace.h>
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#endif
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#endif
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#include <zephyr/debug/coredump.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
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@ -97,7 +98,17 @@ char *z_xtensa_exccause(unsigned int cause_code)
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void z_xtensa_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
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{
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if (esf) {
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/* Don't want to get elbowed by xtensa_switch
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* in between printing registers and dumping them;
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* corrupts backtrace
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*/
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unsigned int key = arch_irq_lock();
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z_xtensa_dump_stack(esf);
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coredump(reason, esf, IS_ENABLED(CONFIG_MULTITHREADING) ? k_current_get() : NULL);
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arch_irq_unlock(key);
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}
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#if defined(CONFIG_XTENSA_ENABLE_BACKTRACE)
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#if XCHAL_HAVE_WINDOWED
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@ -57,6 +57,11 @@ This usually involves the following steps:
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4. Start the debugger corresponding to the target architecture.
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.. note::
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Developers for Intel ADSP CAVS 15-25 platforms using
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``ZEPHYR_TOOLCHAIN_VARIANT=zephyr`` should use the debugger in the
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``xtensa-intel_apl_adsp`` toolchain of the SDK.
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Example
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-------
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@ -13,7 +13,9 @@
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#include <zephyr/logging/log_ctrl.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/fatal.h>
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#ifndef CONFIG_XTENSA
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#include <zephyr/debug/coredump.h>
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#endif
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LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
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@ -122,7 +124,9 @@ void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
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LOG_ERR("Current thread: %p (%s)", thread,
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thread_name_get(thread));
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#ifndef CONFIG_XTENSA
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coredump(reason, esf, thread);
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#endif
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k_sys_fatal_error_handler(reason, esf);
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@ -7,29 +7,66 @@
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import binascii
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import logging
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import struct
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import sys
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from enum import Enum
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from gdbstubs.gdbstub import GdbStub
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logger = logging.getLogger("gdbstub")
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# Matches same in coredump.c
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XTENSA_BLOCK_HDR_DUMMY_SOC = 255
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class XtensaSoc():
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# Must match --soc arg options; see get_soc
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class XtensaSoc(Enum):
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UNKNOWN = 0
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SAMPLE_CONTROLLER = 1
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ESP32 = 2
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INTEL_ADSP_CAVS = 3
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def get_soc_definition(soc):
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# The previous version of this script didn't need to know
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# what toolchain Zephyr was built with; it assumed sample_controller
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# was built with the Zephyr SDK and ESP32 with Espressif's.
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# However, if a SOC can be built by two separate toolchains,
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# there is a chance that the GDBs provided by the toolchains will
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# assign different indices to the same registers. For example, the
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# Intel ADSP family of SOCs can be built with both Zephyr's
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# SDK and Cadence's XCC toolchain. With the same SOC APL,
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# the SDK's GDB assigns PC the index 0, while XCC's GDB assigns
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# it the index 32.
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#
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# (The Espressif value isn't really required, since ESP32 can
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# only be built with Espressif's toolchain, but it's included for
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# completeness.)
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class XtensaToolchain(Enum):
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UNKNOWN = 0
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ZEPHYR = 1
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XCC = 2
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ESPRESSIF = 3
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def get_gdb_reg_definition(soc, toolchain):
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if soc == XtensaSoc.SAMPLE_CONTROLLER:
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return XtensaSoc_SampleController
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return GdbRegDef_Sample_Controller
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elif soc == XtensaSoc.ESP32:
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return XtensaSoc_ESP32
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return GdbRegDef_ESP32
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elif soc == XtensaSoc.INTEL_ADSP_CAVS:
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if toolchain == XtensaToolchain.ZEPHYR:
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return GdbRegDef_Intel_Adsp_CAVS_Zephyr
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elif toolchain == XtensaToolchain.XCC:
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return GdbRegDef_Intel_Adsp_CAVS_XCC
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elif toolchain == XtensaToolchain.ESPRESSIF:
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logger.error("Can't use espressif toolchain with CAVS. " +
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"Use zephyr or xcc instead. Exiting...")
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sys.exit(1)
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else:
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raise NotImplementedError
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else:
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raise NotImplementedError
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class ExceptionCodes():
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class ExceptionCodes(Enum):
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# Matches arch/xtensa/core/fatal.c->z_xtensa_exccause
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ILLEGAL_INSTRUCTION = 0
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# Syscall not fatal
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@ -54,6 +91,9 @@ class ExceptionCodes():
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LOAD_PROHIBITED = 28
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STORE_PROHIBITED = 29
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# Coprocessor disabled spans 32 - 39
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COPROCESSOR_DISABLED_START = 32
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COPROCESSOR_DISABLED_END = 39
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Z_EXCEPT_REASON = 63
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# Others (reserved / unknown) map to default signal
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@ -62,8 +102,8 @@ class GdbStub_Xtensa(GdbStub):
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GDB_SIGNAL_DEFAULT = 7
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# Mapping based on section 4.4.1.5 of the
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# Xtensa ISA Reference Manual
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# (Table 4–64. Exception Causes)
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# Xtensa ISA Reference Manual (Table 4–64. Exception Causes)
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# Somewhat arbitrary; included only because GDB requests it
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GDB_SIGNAL_MAPPING = {
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ExceptionCodes.ILLEGAL_INSTRUCTION: 4,
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ExceptionCodes.INSTR_FETCH_ERROR: 7,
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@ -85,12 +125,14 @@ class GdbStub_Xtensa(GdbStub):
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ExceptionCodes.LOAD_STORE_PRIVILEGE: 11,
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ExceptionCodes.LOAD_PROHIBITED: 11,
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ExceptionCodes.STORE_PROHIBITED: 11,
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ExceptionCodes.Z_EXCEPT_REASON: 6,
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}
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reg_fmt = "<I"
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def __init__(self, logfile, elffile):
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super().__init__(logfile=logfile, elffile=elffile)
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self.registers = None
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self.exception_code = None
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self.gdb_signal = self.GDB_SIGNAL_DEFAULT
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@ -102,48 +144,61 @@ class GdbStub_Xtensa(GdbStub):
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def parse_arch_data_block(self):
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arch_data_blk = self.logfile.get_arch_data()['data']
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# Get SOC in order to get correct format for unpack
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self.soc = bytearray(arch_data_blk)[0]
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self.xtensaSoc = get_soc_definition(self.soc)
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tu = struct.unpack(self.xtensaSoc.ARCH_DATA_BLK_STRUCT, arch_data_blk)
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self.version = struct.unpack('H', arch_data_blk[1:3])[0]
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# Get SOC and toolchain to get correct format for unpack
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self.soc = XtensaSoc(bytearray(arch_data_blk)[0])
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if self.version >= 2:
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self.toolchain = XtensaToolchain(bytearray(arch_data_blk)[3])
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arch_data_blk_regs = arch_data_blk[4:]
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else:
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# v1 only supported ESP32 and sample_controller, each of which
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# only build with one toolchain
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if self.soc == XtensaSoc.ESP32:
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self.toolchain = XtensaToolchain.ESPRESSIF
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else:
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self.toolchain = XtensaToolchain.ZEPHYR
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arch_data_blk_regs = arch_data_blk[3:]
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self.gdb_reg_def = get_gdb_reg_definition(self.soc, self.toolchain)
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tu = struct.unpack(self.gdb_reg_def.ARCH_DATA_BLK_STRUCT_REGS,
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arch_data_blk_regs)
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self.registers = dict()
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self.version = tu[1]
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self.map_registers(tu)
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def map_registers(self, tu):
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i = 2
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for r in self.xtensaSoc.RegNum:
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regNum = r.value
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i = 0
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for r in self.gdb_reg_def.RegNum:
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reg_num = r.value
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# Dummy WINDOWBASE and WINDOWSTART to enable GDB
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# without dumping them and all AR registers;
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# avoids interfering with interrupts / exceptions
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if r == self.xtensaSoc.RegNum.WINDOWBASE:
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self.registers[regNum] = 0
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elif r == self.xtensaSoc.RegNum.WINDOWSTART:
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self.registers[regNum] = 1
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if r == self.gdb_reg_def.RegNum.WINDOWBASE:
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self.registers[reg_num] = 0
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elif r == self.gdb_reg_def.RegNum.WINDOWSTART:
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self.registers[reg_num] = 1
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else:
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if r == self.xtensaSoc.RegNum.EXCCAUSE:
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if r == self.gdb_reg_def.RegNum.EXCCAUSE:
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self.exception_code = tu[i]
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self.registers[regNum] = tu[i]
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self.registers[reg_num] = tu[i]
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i += 1
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def compute_signal(self):
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sig = self.GDB_SIGNAL_DEFAULT
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code = self.exception_code
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code = ExceptionCodes(self.exception_code)
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if code is None:
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sig = self.GDB_SIGNAL_DEFAULT
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# Map cause to GDB signal number
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if code in self.GDB_SIGNAL_MAPPING:
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sig = self.GDB_SIGNAL_MAPPING[code]
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# Coprocessor disabled code spans 32 - 39
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elif 32 <= code <= 39:
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elif ExceptionCodes.COPROCESSOR_DISABLED_START.value <= code <= \
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ExceptionCodes.COPROCESSOR_DISABLED_END.value:
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sig = 8
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self.gdb_signal = sig
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@ -154,18 +209,16 @@ class GdbStub_Xtensa(GdbStub):
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pkt = b''
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GDB_G_PKT_MAX_REG = \
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max([regNum.value for regNum in self.xtensaSoc.RegNum])
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max([reg_num.value for reg_num in self.gdb_reg_def.RegNum])
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# We try to send as many of the registers listed
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# as possible, but we are constrained by the
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# maximum length of the g packet
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while idx <= GDB_G_PKT_MAX_REG and idx * 4 < self.xtensaSoc.SOC_GDB_GPKT_BIN_SIZE:
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while idx <= GDB_G_PKT_MAX_REG and idx * 4 < self.gdb_reg_def.SOC_GDB_GPKT_BIN_SIZE:
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if idx in self.registers:
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bval = struct.pack(self.reg_fmt, self.registers[idx])
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pkt += binascii.hexlify(bval)
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else:
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# Register not in coredump -> unknown value
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# Send in "xxxxxxxx"
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pkt += b'x' * 8
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idx += 1
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@ -174,17 +227,20 @@ class GdbStub_Xtensa(GdbStub):
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def handle_register_single_read_packet(self, pkt):
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# Mark registers as "<unavailable>". 'p' packets are not sent for the registers
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# currently handled in this file so we can safely reply "xxxxxxxx" here.
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self.put_gdb_packet(b'x' * 8)
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# format is pXX, where XX is the hex representation of the idx
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regIdx = int('0x' + pkt[1:].decode('utf8'), 16)
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try:
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bval = struct.pack(self.reg_fmt, self.registers[regIdx])
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self.put_gdb_packet(binascii.hexlify(bval))
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except KeyError:
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self.put_gdb_packet(b'x' * 8)
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# The following classes map registers to their index (idx) on
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# a specific SOC. Since SOCs can have different numbers of
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# registers (e.g. 32 VS 64 ar), the index of a register will
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# differ per SOC. See xtensa_config.c.
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# The following classes map registers to their index used by
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# the GDB of a specific SOC and toolchain. See xtensa_config.c.
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# WARNING: IF YOU CHANGE THE ORDER OF THE REGISTERS IN ONE
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# SOC's MAPPING, YOU MUST CHANGE THE ORDER TO MATCH IN THE OTHERS
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# MAPPING, YOU MUST CHANGE THE ORDER TO MATCH IN THE OTHERS
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# AND IN arch/xtensa/core/coredump.c's xtensa_arch_block.r.
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# See map_registers.
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@ -192,15 +248,18 @@ class GdbStub_Xtensa(GdbStub):
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# values are dummied by this script, they have to be last in the
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# mapping below.
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# sdk-ng -> overlays/xtensa_sample_controller/gdb/gdb/xtensa-config.c
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class XtensaSoc_SampleController:
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ARCH_DATA_BLK_STRUCT = '<BHIIIIIIIIIIIIIIIIIIIIII'
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# This fits the maximum possible register index (110)
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# unlike on ESP32 GDB, there doesn't seem to be an
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# actual hard limit to how big the g packet can be
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# sample_controller is unique to Zephyr SDK
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# sdk-ng -> overlays/xtensa_sample_controller/gdb/gdb/xtensa-config.c
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class GdbRegDef_Sample_Controller:
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ARCH_DATA_BLK_STRUCT_REGS = '<IIIIIIIIIIIIIIIIIIIIII'
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# This fits the maximum possible register index (110).
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# Unlike on ESP32 GDB, there doesn't seem to be an
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# actual hard limit to how big the g packet can be.
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SOC_GDB_GPKT_BIN_SIZE = 444
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class RegNum(Enum):
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PC = 0
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EXCCAUSE = 77
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@ -228,15 +287,17 @@ class XtensaSoc_SampleController:
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WINDOWBASE = 34
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WINDOWSTART = 35
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# ESP32 is unique to espressif toolchain
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# espressif xtensa-overlays -> xtensa_esp32/gdb/gdb/xtensa-config.c
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class XtensaSoc_ESP32:
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ARCH_DATA_BLK_STRUCT = '<BHIIIIIIIIIIIIIIIIIIIIIIIII'
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class GdbRegDef_ESP32:
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ARCH_DATA_BLK_STRUCT_REGS = '<IIIIIIIIIIIIIIIIIIIIIIIII'
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# Maximum index register that can be sent in a group packet is
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# 104, which prevents us from sending An registers directly.
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# We get around this by assigning each An in the dump to ARn
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# and setting WINDOWBASE to 0 and WINDOWSTART to 1; ESP32 GDB
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# will recalculate the corresponding An
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# will recalculate the corresponding An.
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SOC_GDB_GPKT_BIN_SIZE = 420
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class RegNum(Enum):
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@ -267,3 +328,85 @@ class XtensaSoc_ESP32:
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LCOUNT = 67
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WINDOWBASE = 69
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WINDOWSTART = 70
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# sdk-ng -> overlays/xtensa_intel_apl/gdb/gdb/xtensa-config.c
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class GdbRegDef_Intel_Adsp_CAVS_Zephyr:
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ARCH_DATA_BLK_STRUCT_REGS = '<IIIIIIIIIIIIIIIIIIIIIIIII'
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# If you send all the registers below (up to index 173)
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# GDB incorrectly assigns 0 to EXCCAUSE / EXCVADDR... for some
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# reason. Since APL GDB sends p packets for every An register
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# even if it was sent in the g packet, I arbitrarily shrunk the
|
||||
# G packet to include up to A1, which fixed the issue.
|
||||
SOC_GDB_GPKT_BIN_SIZE = 640
|
||||
|
||||
|
||||
class RegNum(Enum):
|
||||
PC = 0
|
||||
EXCCAUSE = 148
|
||||
EXCVADDR = 154
|
||||
SAR = 68
|
||||
PS = 74
|
||||
SCOMPARE1 = 77
|
||||
A0 = 158
|
||||
A1 = 159
|
||||
A2 = 160
|
||||
A3 = 161
|
||||
A4 = 162
|
||||
A5 = 163
|
||||
A6 = 164
|
||||
A7 = 165
|
||||
A8 = 166
|
||||
A9 = 167
|
||||
A10 = 168
|
||||
A11 = 169
|
||||
A12 = 170
|
||||
A13 = 171
|
||||
A14 = 172
|
||||
A15 = 173
|
||||
LBEG = 65
|
||||
LEND = 66
|
||||
LCOUNT = 67
|
||||
WINDOWBASE = 70
|
||||
WINDOWSTART = 71
|
||||
|
||||
|
||||
# Reverse-engineered from:
|
||||
# sof -> src/debug/gdb/gdb.c
|
||||
# sof -> src/arch/xtensa/include/xtensa/specreg.h
|
||||
class GdbRegDef_Intel_Adsp_CAVS_XCC:
|
||||
ARCH_DATA_BLK_STRUCT_REGS = '<IIIIIIIIIIIIIIIIIIIIIIIII'
|
||||
|
||||
# xt-gdb doesn't use the g packet at all
|
||||
SOC_GDB_GPKT_BIN_SIZE = 0
|
||||
|
||||
|
||||
class RegNum(Enum):
|
||||
PC = 32
|
||||
EXCCAUSE = 744
|
||||
EXCVADDR = 750
|
||||
SAR = 515
|
||||
PS = 742
|
||||
SCOMPARE1 = 524
|
||||
A0 = 256
|
||||
A1 = 257
|
||||
A2 = 258
|
||||
A3 = 259
|
||||
A4 = 260
|
||||
A5 = 261
|
||||
A6 = 262
|
||||
A7 = 263
|
||||
A8 = 264
|
||||
A9 = 265
|
||||
A10 = 266
|
||||
A11 = 267
|
||||
A12 = 268
|
||||
A13 = 269
|
||||
A14 = 270
|
||||
A15 = 271
|
||||
LBEG = 512
|
||||
LEND = 513
|
||||
LCOUNT = 514
|
||||
WINDOWBASE = 584
|
||||
WINDOWSTART = 585
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
|
||||
config SOC_FAMILY_INTEL_ADSP
|
||||
select WINSTREAM
|
||||
select ARCH_SUPPORTS_COREDUMP
|
||||
bool
|
||||
|
||||
if SOC_FAMILY_INTEL_ADSP
|
||||
|
|
|
|||
|
|
@ -22,3 +22,16 @@ zephyr_library_sources_ifdef(
|
|||
CONFIG_DEBUG_COREDUMP_BACKEND_FLASH_PARTITION
|
||||
coredump_backend_flash_partition.c
|
||||
)
|
||||
|
||||
# @Intent: Set XTENSA_TOOLCHAIN_VARIANT macro required for Xtensa coredump
|
||||
if(CONFIG_XTENSA)
|
||||
if(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "zephyr")
|
||||
zephyr_compile_options(-DXTENSA_TOOLCHAIN_VARIANT=1)
|
||||
elseif(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "xcc")
|
||||
zephyr_compile_options(-DXTENSA_TOOLCHAIN_VARIANT=2)
|
||||
elseif(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "espressif")
|
||||
zephyr_compile_options(-DXTENSA_TOOLCHAIN_VARIANT=3)
|
||||
else()
|
||||
zephyr_compile_options(-DXTENSA_TOOLCHAIN_VARIANT=0)
|
||||
endif()
|
||||
endif()
|
||||
|
|
|
|||
|
|
@ -13,9 +13,14 @@ void func_3(uint32_t *addr)
|
|||
#if defined(CONFIG_BOARD_M2GL025_MIV) || \
|
||||
defined(CONFIG_BOARD_HIFIVE1) || \
|
||||
defined(CONFIG_BOARD_LONGAN_NANO) || \
|
||||
defined(CONFIG_BOARD_LONGAN_NANO_LITE)
|
||||
defined(CONFIG_BOARD_LONGAN_NANO_LITE) || \
|
||||
defined(CONFIG_SOC_FAMILY_INTEL_ADSP)
|
||||
ARG_UNUSED(addr);
|
||||
/* Call k_panic() directly so Renode doesn't pause execution */
|
||||
/* Call k_panic() directly so Renode doesn't pause execution.
|
||||
* Needed on ADSP as well, since null pointer derefence doesn't
|
||||
* fault as the lowest memory region is writable. SOF uses k_panic
|
||||
* a lot, so it's good to check that it causes a coredump.
|
||||
*/
|
||||
k_panic();
|
||||
#elif !defined(CONFIG_CPU_CORTEX_M)
|
||||
/* For null pointer reference */
|
||||
|
|
|
|||
Loading…
Reference in a new issue