drivers: hwinfo: modification into hwinfo_get_reset_cause()
add retrieve flag SB into hwinfo_get_reset_cause() add Clear flag SB into clear_reset_cause() Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
This commit is contained in:
parent
cbd9e2172f
commit
3392eb6af3
1 changed files with 35 additions and 0 deletions
|
|
@ -10,6 +10,7 @@
|
||||||
#if defined(CONFIG_SOC_SERIES_STM32H5X)
|
#if defined(CONFIG_SOC_SERIES_STM32H5X)
|
||||||
#include <stm32_ll_icache.h>
|
#include <stm32_ll_icache.h>
|
||||||
#endif /* CONFIG_SOC_SERIES_STM32H5X */
|
#endif /* CONFIG_SOC_SERIES_STM32H5X */
|
||||||
|
#include <stm32_ll_pwr.h>
|
||||||
#include <zephyr/drivers/hwinfo.h>
|
#include <zephyr/drivers/hwinfo.h>
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <zephyr/sys/byteorder.h>
|
#include <zephyr/sys/byteorder.h>
|
||||||
|
|
@ -113,6 +114,28 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM4)
|
||||||
|
if (LL_PWR_CPU2_IsActiveFlag_SB()) {
|
||||||
|
flags |= RESET_LOW_POWER_WAKE;
|
||||||
|
}
|
||||||
|
#elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM7)
|
||||||
|
if (LL_PWR_CPU_IsActiveFlag_SB()) {
|
||||||
|
flags |= RESET_LOW_POWER_WAKE;
|
||||||
|
}
|
||||||
|
#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
|
||||||
|
if (LL_PWR_MCU_IsActiveFlag_SB()) {
|
||||||
|
flags |= RESET_LOW_POWER_WAKE;
|
||||||
|
}
|
||||||
|
#elif defined(CONFIG_SOC_SERIES_STM32WLX) || defined(CONFIG_SOC_SERIES_STM32WBX)
|
||||||
|
if (LL_PWR_IsActiveFlag_C1SB()) {
|
||||||
|
flags |= RESET_LOW_POWER_WAKE;
|
||||||
|
}
|
||||||
|
#elif defined(PWR_FLAG_SB)
|
||||||
|
if (LL_PWR_IsActiveFlag_SB()) {
|
||||||
|
flags |= RESET_LOW_POWER_WAKE;
|
||||||
|
}
|
||||||
|
#endif /* PWR_FLAG_SB */
|
||||||
|
|
||||||
*cause = flags;
|
*cause = flags;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
@ -122,6 +145,18 @@ int z_impl_hwinfo_clear_reset_cause(void)
|
||||||
{
|
{
|
||||||
LL_RCC_ClearResetFlags();
|
LL_RCC_ClearResetFlags();
|
||||||
|
|
||||||
|
#if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM4)
|
||||||
|
LL_PWR_ClearFlag_CPU2();
|
||||||
|
#elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM7)
|
||||||
|
LL_PWR_ClearFlag_CPU();
|
||||||
|
#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
|
||||||
|
LL_PWR_ClearFlag_MCU();
|
||||||
|
#elif defined(CONFIG_SOC_SERIES_STM32WLX) || defined(CONFIG_SOC_SERIES_STM32WBX)
|
||||||
|
LL_PWR_ClearFlag_C1STOP_C1STB();
|
||||||
|
#elif defined(PWR_FLAG_SB)
|
||||||
|
LL_PWR_ClearFlag_SB();
|
||||||
|
#endif /* PWR_FLAG_SB */
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue