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soc: kb1200 soc

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Add support for ENE KB1200 SOC

Signed-off-by: Steven Chang <steven@ene.com.tw>
This commit is contained in:
Steven Chang 2024-03-15 10:46:26 +08:00 committed by Fabio Baltieri
parent 9897761aa5
commit 388091a4af
17 changed files with 625 additions and 0 deletions
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7
soc/ene/kb1200/CMakeLists.txt Normal file
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# Copyright (c) 2023 ENE Technology Inc.
# SPDX-License-Identifier: Apache-2.0
zephyr_library()
zephyr_library_sources(soc.c)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

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soc/ene/kb1200/Kconfig Normal file
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# Copyright (c) 2024 ENE Technology Inc.
# SPDX-License-Identifier: Apache-2.0
config SOC_KB1200
select ARM
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU

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soc/ene/kb1200/Kconfig.defconfig Normal file
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# Copyright (c) 2023 ENE Technology Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_KB1200
config NUM_IRQS
default 64
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config BUILD_OUTPUT_BIN
default y
config BUILD_OUTPUT_HEX
default y
endif # SOC_KB1200

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soc/ene/kb1200/Kconfig.soc Normal file
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# Copyright (c) 2024 ENE Technology Inc.
# SPDX-License-Identifier: Apache-2.0
config SOC_KB1200
bool
help
ENE KB1200
config SOC
default "kb1200" if SOC_KB1200

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soc/ene/kb1200/reg/adc.h Normal file
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/*
* Copyright (c) 2024 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ENE_KB1200_ADC_H
#define ENE_KB1200_ADC_H
/**
* Structure type to access Analog to Digital Converter (ADC).
*/
struct adc_regs {
volatile uint32_t ADCCFG; /* Configuration Register */
volatile uint32_t Reserved[3]; /* Reserved */
volatile uint32_t ADCDAT[14]; /* Data Register */
};
#define ADC_CHANNEL_BIT_POS 16
#define ADC_CHANNEL_BIT_MASK 0x3FFF0000
#define ADC_RESOLUTION 10 /* Unit:bits */
#define ADC_VREF_ANALOG 3300 /* Unit:mV */
#define ADC_MAX_CHAN 14
#define ADC_FUNCTION_ENABLE 0x0001
#define ADC_INVALID_VALUE 0x8000
#define ADC_WAIT_TIME 100
#define ADC_WAIT_CNT 100
#endif /* ENE_KB1200_ADDA_H */

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soc/ene/kb1200/reg/fsmbm.h Normal file
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/*
* Copyright (c) 2024 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ENE_KB1200_FSMBM_H
#define ENE_KB1200_FSMBM_H
/**
* Structure type to access Flexible SMBus Master (FSMBM).
*/
struct fsmbm_regs {
volatile uint32_t FSMBMCFG; /* Configuration Register */
volatile uint8_t FSMBMIE; /* Interrupt Enable Register */
volatile uint8_t Reserved0[3];
volatile uint8_t FSMBMPF; /* Event Pending Flag Register */
volatile uint8_t Reserved1[3];
volatile uint8_t FSMBMFRT; /* Protocol Control Register */
volatile uint8_t Reserved2[3];
volatile uint16_t FSMBMPEC; /* PEC Value Register */
volatile uint16_t Reserved3;
volatile uint8_t FSMBMSTS; /* Status Register */
volatile uint8_t Reserved4[3];
volatile uint8_t FSMBMADR; /* Slave Address Register */
volatile uint8_t Reserved5[3];
volatile uint8_t FSMBMCMD; /* Command Register */
volatile uint8_t Reserved6[3];
volatile uint8_t FSMBMDAT[32]; /* Data Register */
volatile uint8_t FSMBMPRTC_P; /* Protocol Register */
volatile uint8_t FSMBMPRTC_C; /* Protocol Register */
volatile uint16_t Reserved7;
volatile uint8_t FSMBMNADR; /* HostNotify Slave Address Register */
volatile uint8_t Reserved8[3];
volatile uint16_t FSMBMNDAT; /* HostNotify Data Register */
volatile uint16_t Reserved9;
};
#define FSMBM_NUM 10
/* data->state */
#define STATE_IDLE 0
#define STATE_SENDING 1
#define STATE_RECEIVING 2
#define STATE_COMPLETE 3
/* PROTOCOL */
#define FLEXIBLE_PROTOCOL 0x7F
/* Error code */
#define FSMBM_NO_ERROR 0x00
#define FSMBM_DEVICE_ADDR_NO_ACK 0x10
#define FSMBM_CMD_NO_ACK 0x12
#define FSMBM_DEVICE_DATA_NO_ACK 0x13
#define FSMBM_LOST_ARBITRATION 0x17
#define FSMBM_SMBUS_TIMEOUT 0x18
#define FSMBM_UNSUPPORTED_PRTC 0x19
#define FSMBM_SMBUS_BUSY 0x1A
#define FSMBM_STOP_FAIL 0x1E
#define FSMBM_PEC_ERROR 0x1F
/* Packet Form */
#define ___NONE 0x00
#define ___STOP 0x01
#define __PEC_ 0x02
#define __PEC_STOP 0x03
#define _CNT__ 0x04
#define _CNT__STOP 0x05
#define _CNT_PEC_ 0x06
#define _CNT_PEC_STOP 0x07
#define CMD___ 0x08
#define CMD___STOP 0x09
#define CMD__PEC_ 0x0A
#define CMD__PEC_STOP 0x0B
#define CMD_CNT__ 0x0C
#define CMD_CNT__STOP 0x0D
#define CMD_CNT_PEC_ 0x0E
#define CMD_CNT_PEC_STOP 0x0F
#define FLEXIBLE_CMD 0x08
#define FLEXIBLE_CNT 0x04
#define FLEXIBLE_PEC 0x02
#define FLEXIBLE_STOP 0x01
/* HW */
#define FSMBM_BUFFER_SIZE 0x20
#define FSMBM_MAXCNT 0xFF
#define FSMBM_WRITE 0x00
#define FSMBM_READ 0x01
/* Clock Setting = 1 / (1u + (1u * N)) ,50% Duty Cycle */
#define FSMBM_CLK_1M 0x0000
#define FSMBM_CLK_500K 0x0101
#define FSMBM_CLK_333K 0x0202
#define FSMBM_CLK_250K 0x0303
#define FSMBM_CLK_200K 0x0404
#define FSMBM_CLK_167K 0x0505
#define FSMBM_CLK_143K 0x0606
#define FSMBM_CLK_125K 0x0707
#define FSMBM_CLK_111K 0x0808
#define FSMBM_CLK_100K 0x0909
#define FSMBM_CLK_91K 0x0A0A
#define FSMBM_CLK_83K 0x0B0B
#define FSMBM_CLK_71K 0x0D0D
#define FSMBM_CLK_63K 0x0F0F
#define FSMBM_CLK_50K 0x1313
#define FSMBM_CLK_40K 0x1818
#define FSMBM_CLK_30K 0x2020
#define FSMBM_CLK_20K 0x3131
#define FSMBM_CLK_10K 0x6363
/* Other(non 50% Duty Cycle) */
#define FSMBM_CLK_400K 0x0102
#define FSMBM_COMPLETE_EVENT 0x01
#define FSMBM_HOST_NOTIFY_EVENT 0x02
#define FSMBM_BLOCK_FINISH_EVENT 0x04
#define FSMBM_FUNCTION_ENABLE 0x01
#define FSMBM_TIMEOUT_ENABLE 0x02
#define FSMBM_HW_RESET 0x10
#define FSMBM_CLK_POS 16
#define FSMBM_CLK_MASK 0xFFFF
#define FSMBM_STS_MASK 0x1F
#endif /* ENE_KB1200_FSMBM_H */

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soc/ene/kb1200/reg/gcfg.h Normal file
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/*
* Copyright (c) 2023 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ENE_KB1200_GCFG_H
#define ENE_KB1200_GCFG_H
/**
* Structure type to access General Configuration (GCFG).
*/
struct gcfg_regs {
volatile uint8_t IDV; /*Version ID Register */
volatile uint8_t Reserved0; /*Reserved */
volatile uint16_t IDC; /*Chip ID Register */
volatile uint32_t FWID; /*Firmware ID Register */
volatile uint32_t MCURST; /*MCU Reset Control Register */
volatile uint32_t RSTFLAG; /*Reset Pending Flag Register */
volatile uint32_t GPIOALT; /*GPIO Alternate Register */
volatile uint8_t VCCSTA; /*VCC Status Register */
volatile uint8_t Reserved1[3]; /*Reserved */
volatile uint16_t GPIOMUX; /*GPIO MUX Control Register */
volatile uint16_t Reserved2; /*Reserved */
volatile uint16_t I2CSPMS; /*I2CS Pin Map Selection Register */
volatile uint16_t Reserved3; /*Reserved */
volatile uint8_t CLKCFG; /*Clock Configuration Register */
volatile uint8_t Reserved4[3]; /*Reserved */
volatile uint32_t DPLLFREQ; /*DPLL Frequency Register */
volatile uint32_t Reserved5; /*Reserved */
volatile uint32_t GCFGMISC; /*Misc. Register */
volatile uint8_t EXTIE; /*Extended Command Interrupt Enable Register */
volatile uint8_t Reserved6[3]; /*Reserved */
volatile uint8_t EXTPF; /*Extended Command Pending Flag Register */
volatile uint8_t Reserved7[3]; /*Reserved */
volatile uint32_t EXTARG; /*Extended Command Argument0/1/2 Register */
volatile uint8_t EXTCMD; /*Extended Command Port Register */
volatile uint8_t Reserved8[3]; /*Reserved */
volatile uint32_t ADCOTR; /*ADCO Register */
volatile uint32_t IDSR; /*IDSR Register */
volatile uint32_t Reserved9[14]; /*Reserved */
volatile uint32_t TRAPMODE;
volatile uint32_t CLK1UCFG;
volatile uint32_t LDO15TRIM;
volatile uint32_t Reserved10;
volatile uint32_t WWTR;
volatile uint32_t ECMISC2;
volatile uint32_t DPLLCTRL;
};
#define GCFG_CLKCFG_96M 0x00000004
#define GCFG_CLKCFG_48M 0x00000014
#define GCFG_CLKCFG_24M 0x00000024
#endif /* ENE_KB1200_GCFG_H */

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soc/ene/kb1200/reg/gpio.h Normal file
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/*
* Copyright (c) 2023 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ENE_KB1200_GPIO_H
#define ENE_KB1200_GPIO_H
/**
* Structure type to access General Purpose Input/Output (GPIO).
*/
struct gpio_regs {
volatile uint32_t GPIOFS; /*Function Selection Register */
volatile uint32_t Reserved1[3];
volatile uint32_t GPIOOE; /*Output Enable Register */
volatile uint32_t Reserved2[3];
volatile uint32_t GPIOD; /*Output Data Register */
volatile uint32_t Reserved3[3];
volatile uint32_t GPIOIN; /*Input Data Register */
volatile uint32_t Reserved4[3];
volatile uint32_t GPIOPU; /*Pull Up Register */
volatile uint32_t Reserved5[3];
volatile uint32_t GPIOOD; /*Open Drain Register */
volatile uint32_t Reserved6[3];
volatile uint32_t GPIOIE; /*Input Enable Register */
volatile uint32_t Reserved7[3];
volatile uint32_t GPIODC; /*Driving Control Register */
volatile uint32_t Reserved8[3];
volatile uint32_t GPIOLV; /*Low Voltage Mode Enable Register */
volatile uint32_t Reserved9[3];
volatile uint32_t GPIOPD; /*Pull Down Register */
volatile uint32_t Reserved10[3];
volatile uint32_t GPIOFL; /*Function Lock Register */
volatile uint32_t Reserved11[3];
};
#define NUM_KB1200_GPIO_PORTS 4
/*-- Constant Define --------------------------------------------*/
#define GPIO00_PWMLED0_PWM8 0x00
#define GPIO01_SERRXD1_UARTSIN 0x01
#define GPIO03_SERTXD1_UARTSOUT 0x03
#define GPIO22_ESBDAT_PWM9 0x22
#define GPIO28_32KOUT_SERCLK2 0x28
#define GPIO36_UARTSOUT_SERTXD2 0x36
#define GPIO5C_KSO6_P80DAT 0x5C
#define GPIO5D_KSO7_P80CLK 0x5D
#define GPIO5E_KSO8_SERRXD1 0x5E
#define GPIO5F_KSO9_SERTXD1 0x5F
#define GPIO71_SDA8_UARTRTS 0x71
#define GPIO38_SCL4_PWM1 0x38
#endif /* ENE_KB1200_GPIO_H */

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soc/ene/kb1200/reg/gptd.h Normal file
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/*
* Copyright (c) 2023 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ENE_KB1200_GPTD_H
#define ENE_KB1200_GPTD_H
/**
* Structure type to access GPIO Trigger Detector (GPTD).
*/
struct gptd_regs {
volatile uint32_t GPTDIE; /*Interrupt Enable Register */
volatile uint32_t Reserved1[3];
volatile uint32_t GPTDPF; /*Event Pending Flag Register */
volatile uint32_t Reserved2[3];
volatile uint32_t GPTDCHG; /*Change Trigger Register */
volatile uint32_t Reserved3[3];
volatile uint32_t GPTDEL; /*Level/Edge Trigger Register */
volatile uint32_t Reserved4[3];
volatile uint32_t GPTDPS; /*Polarity Selection Register */
volatile uint32_t Reserved5[3];
volatile uint32_t GPTDWE; /*WakeUP Enable Register */
volatile uint32_t Reserved6[3];
};
#endif /* ENE_KB1200_GPTD_H */

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soc/ene/kb1200/reg/pmu.h Normal file
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/*
* Copyright (c) 2023 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ENE_KB1200_PMU_H
#define ENE_KB1200_PMU_H
/**
* Structure type to access Power Management Unit (PMU).
*/
struct pmu_regs {
volatile uint8_t PMUIDLE; /*IDLE wakeup by Interrupt Register */
volatile uint8_t Reserved0[3]; /*Reserved */
volatile uint32_t PMUSTOP; /*STOP Wakeup Source Register */
volatile uint8_t PMUSTOPC; /*STOP Control Register */
volatile uint8_t Reserved1[3]; /*Reserved */
volatile uint8_t PMUCTRL; /*Control Register */
volatile uint8_t Reserved2[3]; /*Reserved */
volatile uint8_t PMUSTAF; /*Status Flag */
volatile uint8_t Reserved3[3]; /*Reserved */
};
/* STOP Wakeup Source */
#define PMU_STOP_WU_GPTD 0x00000001
#define PMU_STOP_WU_VC0 0x00000002
#define PMU_STOP_WU_VC1 0x00000004
#define PMU_STOP_WU_IKB 0x00000010
#define PMU_STOP_WU_WDT 0x00000100
#define PMU_STOP_WU_HIBTMR 0x00000400
#define PMU_STOP_WU_eSPI 0x00010000
#define PMU_STOP_WU_SPIS 0x00010000
#define PMU_STOP_WU_I2CD32 0x00020000
#define PMU_STOP_WU_EDI32 0x00040000
#define PMU_STOP_WU_SWD 0x00080000
#define PMU_STOP_WU_ITIM 0x00100000
#define PMU_STOP_WU_I2CS0 0x01000000
#define PMU_STOP_WU_I2CS1 0x02000000
#define PMU_STOP_WU_I2CS2 0x04000000
#define PMU_STOP_WU_I2CS3 0x08000000
#define PMU_IDLE_WU_ENABLE 0x00000001
#endif /* ENE_KB1200_PMU_H */

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/*
* Copyright (c) 2024 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ENE_KB1200_PWM_H
#define ENE_KB1200_PWM_H
/**
* Structure type to access Pulse Width Modulation (PWM).
*/
struct pwm_regs {
volatile uint16_t PWMCFG; /*Configuration Register */
volatile uint16_t Reserved0; /*Reserved */
volatile uint16_t PWMHIGH; /*High Length Register */
volatile uint16_t Reserved1; /*Reserved */
volatile uint16_t PWMCYC; /*Cycle Length Register */
volatile uint16_t Reserved2; /*Reserved */
volatile uint32_t PWMCHC; /*Current High/Cycle Length Register */
};
#define PWM_SOURCE_CLK_32M 0x0000
#define PWM_SOURCE_CLK_1M 0x4000
#define PWM_SOURCE_CLK_32_768K 0x8000
#define PWM_PRESCALER_BIT_S 8
#define PWM_RULE0 0x0000
#define PWM_RULE1 0x0080
#define PWM_PUSHPULL 0x0000
#define PWM_OPENDRAIN 0x0002
#define PWM_ENABLE 0x0001
#define PWM_INPUT_FREQ_HI 32000000u
#define PWM_MAX_PRESCALER (1UL << (6))
#define PWM_MAX_CYCLES (1UL << (14))
#endif /* ENE_KB1200_PWM_H */

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/*
* Copyright (c) 2023 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ENE_KB1200_SER_H
#define ENE_KB1200_SER_H
/**
* Structure type to access Serial Port Interface (SER).
*/
struct serial_regs {
volatile uint32_t SERCFG; /*Configuration Register */
volatile uint32_t SERIE; /*Interrupt Enable Register */
volatile uint32_t SERPF; /*Pending flag Register */
volatile uint32_t SERSTS; /*Status Register */
volatile uint32_t SERRBUF; /*Rx Data Buffer Register */
volatile uint32_t SERTBUF; /*Tx Data Buffer Register */
volatile uint32_t SERCTRL; /*Control Register */
};
#define DIVIDER_BASE_CLK 24000000
#define SERCTRL_MODE0 0 /* shift */
#define SERCTRL_MODE1 1 /* 8-bit */
#define SERCTRL_MODE2 2 /* 9-bit */
#define SERCTRL_MODE3 3 /* 9-bit */
#define SERCFG_RX_ENABLE 0x01
#define SERCFG_TX_ENABLE 0x02
#define SERCFG_PARITY_NONE 0
#define SERCFG_PARITY_ODD 1
#define SERCFG_PARITY_EVEN 3
/* Pending Flag */
#define SERPF_RX_CNT_FULL 0x01
#define SERPF_TX_EMPTY 0x02
#define SERPF_RX_ERROR 0x04
/* Interrupt Enable */
#define SERIE_RX_ENABLE 0x01
#define SERIE_TX_ENABLE 0x02
#define SERIE_RX_ERROR 0x04
/* Status Flag */
#define SERSTS_FRAME_ERROR 0x0200
#define SERSTS_PARITY_ERROR 0x0100
#define SERSTS_RX_TIMEOUT 0x0080
#define SERSTS_RX_BUSY 0x0040
#define SERSTS_RX_OVERRUN 0x0020
#define SERSTS_RX_EMPTY 0x0010
#define SERSTS_TX_BUSY 0x0004
#define SERSTS_TX_OVERRUN 0x0002
#define SERSTS_TX_FULL 0x0001
#endif /* ENE_KB1200_SER_H */

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soc/ene/kb1200/reg/tacho.h Normal file
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/*
* Copyright (c) 2024 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ENE_KB1200_TACHO_H
#define ENE_KB1200_TACHO_H
/**
* brief Structure type to access TACHO.
*/
struct tacho_regs {
volatile uint16_t TACHOCFG; /*Configuration Register */
volatile uint16_t Reserved0; /*Reserved */
volatile uint8_t TACHOIE; /*Interrupt Enable Register */
volatile uint8_t Reserved1[3]; /*Reserved */
volatile uint8_t TACHOPF; /*Event Pending Flag Register */
volatile uint8_t Reserved2[3]; /*Reserved */
volatile uint16_t TACHOCV; /*TACHO0 Counter Value Register */
volatile uint16_t Reserved3; /*Reserved */
};
#define TACHO_CNT_MAX_VALUE 0x7FFF
#define TACHO_TIMEOUT_EVENT 0x02
#define TACHO_UPDATE_EVENT 0x01
#define TACHO_MONITOR_CLK_64US 0
#define TACHO_MONITOR_CLK_16US 1
#define TACHO_MONITOR_CLK_8US 2
#define TACHO_MONITOR_CLK_2US 3
#define TACHO_FUNCTION_ENABLE 0x0001
#define TACHO_RING_EDGE_SAMPLE 0x0000
#define TACHO_EDGE_CHANGE_SAMPLE 0x0080
#define TACHO_FILTER_ENABLE 0x8000
#endif /* ENE_KB1200_TACHO_H */

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soc/ene/kb1200/reg/wdt.h Normal file
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/*
* Copyright (c) 2024 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ENE_KB1200_WDT_H
#define ENE_KB1200_WDT_H
/**
* brief Structure type to access Watch Dog Timer (WDT).
*/
struct wdt_regs {
volatile uint8_t WDTCFG; /*Configuration Register */
volatile uint8_t WDTCFG_T; /*Configuration Reset Type Register */
volatile uint16_t Reserved0; /*Reserved */
volatile uint8_t WDTIE; /*Interrupt Enable Register */
volatile uint8_t Reserved1[3]; /*Reserved */
volatile uint8_t WDTPF; /*Event Pending Flag Register */
volatile uint8_t Reserved2[3]; /*Reserved */
volatile uint16_t WDTM; /*WDT Match Value Register */
volatile uint16_t Reserved3; /*Reserved */
volatile uint8_t WDTSCR[4]; /*FW Scratch(4 bytes) Register */
};
#define WDT_MIN_CNT 3U
#define WDT_SAMPLE_TIME 31.25
#define WDT_RESET_WHOLE_CHIP_WO_GPIO 0
#define WDT_RESET_WHOLE_CHIP 1
#define WDT_RESET_ONLY_MCU 2
#define WDT_DISABLE_PASSWORD 0x90
#define WDT_ADCO32K 0x00
#define WDT_PHER32K 0x02
#define WDT_FUNCTON_ENABLE 0x01
#define WDT_HALF_WAY_EVENT 0x01
#define WDT_RESET_EVENT 0x02
#endif /* ENE_KB1200_WDT_H */

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/*
* Copyright (c) 2023 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/devicetree.h>
#include <reg/pmu.h>
#include <reg/gcfg.h>
#define PMU_BASE DT_REG_ADDR(DT_NODELABEL(pmu))
#define GCFG_BASE DT_REG_ADDR(DT_NODELABEL(gcfg))
static void pmu_init(void)
{
struct pmu_regs *pmu = ((struct pmu_regs *)PMU_BASE);
/* Interrupt Event Wakeup from IDLE mode Enable */
pmu->PMUIDLE |= PMU_IDLE_WU_ENABLE;
/* GPTD wake up from STOP mode enable. */
pmu->PMUSTOP |= PMU_STOP_WU_GPTD;
/* SWD EDI32 wake up from STOP mode enable */
pmu->PMUSTOP |= (PMU_STOP_WU_EDI32 | PMU_STOP_WU_SWD);
}
static void clock_init(void)
{
struct gcfg_regs *gcfg = ((struct gcfg_regs *)GCFG_BASE);
if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 96000000) {
/* AHB/APB clock select 96MHz/48MHz */
gcfg->CLKCFG = GCFG_CLKCFG_96M;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 48000000) {
/* AHB/APB clock select 48MHz/24MHz */
gcfg->CLKCFG = GCFG_CLKCFG_48M;
} else {
/* AHB/APB clock select 24MHz/12MHz */
gcfg->CLKCFG = GCFG_CLKCFG_24M;
}
}
static int kb1200_init(void)
{
clock_init();
pmu_init();
return 0;
}
SYS_INIT(kb1200_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

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/*
* Copyright (c) 2023 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _KB1200_SOC_H_
#define _KB1200_SOC_H_
#include <cmsis_core_m_defaults.h>
#endif /* _KB1200_SOC_H_ */

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soc/ene/kb1200/soc.yml Normal file
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socs:
- name: kb1200