diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi
index 6f14e2369bf..5036493e567 100644
--- a/dts/arm/st/h5/stm32h5.dtsi
+++ b/dts/arm/st/h5/stm32h5.dtsi
@@ -457,6 +457,32 @@
 			status = "disabled";
 		};
 
+		i3c1: i3c@40005c00 {
+			compatible = "st,stm32-i3c";
+			reg = <0x40005c00 0x400>;
+			interrupts = <123 0>, <124 0>;
+			interrupt-names = "event", "error";
+			#address-cells = <3>;
+			#size-cells = <0>;
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
+			resets = <&rctl STM32_RESET(APB1L, 23U)>;
+			zephyr,pm-device-runtime-auto;
+			status = "disabled";
+		};
+
+		i3c2: i3c@44003000 {
+			compatible = "st,stm32-i3c";
+			reg = <0x44003000 0x400>;
+			interrupts = <131 0>, <132 0>;
+			interrupt-names = "event", "error";
+			#address-cells = <3>;
+			#size-cells = <0>;
+			clocks = <&rcc STM32_CLOCK(APB3, 9U)>;
+			resets = <&rctl STM32_RESET(APB3, 9U)>;
+			zephyr,pm-device-runtime-auto;
+			status = "disabled";
+		};
+
 		spi1: spi@40013000 {
 			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
 			#address-cells = <1>;
diff --git a/dts/bindings/i3c/st,stm32-i3c.yaml b/dts/bindings/i3c/st,stm32-i3c.yaml
new file mode 100644
index 00000000000..75395c31487
--- /dev/null
+++ b/dts/bindings/i3c/st,stm32-i3c.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2024 EXALT Technologies.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32H5 I3C controller
+
+compatible: "st,stm32-i3c"
+
+include: [i3c-controller.yaml, pinctrl-device.yaml, reset-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  resets:
+    required: true
+
+  dmas:
+    description: |
+      Optional DMA channel specifier, required for DMA transactions.
+
+  dma-names:
+    description: |
+      DMA channel name. If DMA should be used, expected value is "rx" "tx" "tc" "rs".
+
+      For example
+         dma-names = "rx", "tx", "tc", "rs";