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ITE: it82xx2.dtsi: add watchdog device node

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With this change, it82xx2 series can use the same
watchdog driver as it81xx2 series.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This commit is contained in:
Ruibin Chang 2022-09-29 17:48:27 +08:00 committed by Anas Nashif
parent b9a7340ded
commit 3fb097c1ff
4 changed files with 24 additions and 21 deletions
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2
dts/riscv/ite/it81xx2.dtsi
View file

@ -593,7 +593,7 @@
twd0: watchdog@f01f00 {
compatible = "ite,it8xxx2-watchdog";
reg = <0x00f01f00 0x0062>;
reg = <0x00f01f00 0x000f>;
interrupts = <IT8XXX2_IRQ_TIMER1 IRQ_TYPE_EDGE_RISING /* Warning timer */
IT8XXX2_IRQ_TIMER2 IRQ_TYPE_EDGE_RISING>; /* One shot timer */
interrupt-parent = <&intc>;

8
dts/riscv/ite/it82xx2.dtsi
View file

@ -15,6 +15,14 @@
interrupt-controller;
reg = <0x00f03f00 0x0100>;
};
twd0: watchdog@f01f80 {
compatible = "ite,it8xxx2-watchdog";
reg = <0x00f01f80 0x000f>;
interrupts = <IT8XXX2_IRQ_TIMER1 IRQ_TYPE_EDGE_RISING /* Warning timer */
IT8XXX2_IRQ_TIMER2 IRQ_TYPE_EDGE_RISING>; /* One shot timer */
interrupt-parent = <&intc>;
};
};
};

15
soc/riscv/riscv-ite/common/check_regs.c
View file

@ -147,6 +147,21 @@ IT8XXX2_REG_OFFSET_CHECK(adc_it8xxx2_regs, adc_vchs_ctrl[0].VCHCTL, 0x60);
IT8XXX2_REG_OFFSET_CHECK(adc_it8xxx2_regs, adc_vchs_ctrl[2].VCHDATM, 0x67);
IT8XXX2_REG_OFFSET_CHECK(adc_it8xxx2_regs, ADCDVSTS2, 0x6c);
/* Watchdog register structure check */
IT8XXX2_REG_SIZE_CHECK(wdt_it8xxx2_regs, 0x0f);
IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ETWCFG, 0x01);
IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET1PSR, 0x02);
IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET1CNTLHR, 0x03);
IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET1CNTLLR, 0x04);
IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ETWCTRL, 0x05);
IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, EWDCNTLR, 0x06);
IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, EWDKEYR, 0x07);
IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, EWDCNTHR, 0x09);
IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET2PSR, 0x0a);
IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET2CNTLHR, 0x0b);
IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET2CNTLLR, 0x0c);
IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET2CNTLH2R, 0x0e);
/* SPISC register structure check */
IT8XXX2_REG_SIZE_CHECK(spisc_it8xxx2_regs, 0x28);
IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_IMR, 0x04);

20
soc/riscv/riscv-ite/common/chip_chipregs.h
View file

@ -334,26 +334,6 @@ struct wdt_it8xxx2_regs {
volatile uint8_t reserved3;
/* 0x00E: External Timer2 Counter High Byte2 */
volatile uint8_t ET2CNTLH2R;
/* 0x00F~0x03F: Reserved4 */
volatile uint8_t reserved4[49];
/* 0x040: External Timer1 Counter Observation Low Byte */
volatile uint8_t ET1CNTOLR;
/* 0x041: External Timer1 Counter Observation High Byte */
volatile uint8_t ET1CNTOHR;
/* 0x042~0x043: Reserved5 */
volatile uint8_t reserved5[2];
/* 0x044: External Timer1 Counter Observation Low Byte */
volatile uint8_t ET2CNTOLR;
/* 0x045: External Timer1 Counter Observation High Byte */
volatile uint8_t ET2CNTOHR;
/* 0x046: External Timer1 Counter Observation High Byte2 */
volatile uint8_t ET2CNTOH2R;
/* 0x047~0x05F: Reserved6 */
volatile uint8_t reserved6[25];
/* 0x060: External WDT Counter Observation Low Byte */
volatile uint8_t EWDCNTOLR;
/* 0x061: External WDT Counter Observation High Byte */
volatile uint8_t EWDCNTOHR;
};
#endif /* !__ASSEMBLER__ */