boards: s32z2xx: enable flash controller QSPI

The on-board S26HS512T 512M-bit HyperFlash memory is connected to
the QSPI controller port A1.
This board configuration selects it as the default flash controller.

Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>

boards/nxp/s32z2xxdc2/doc/index.rst

@@ -62,6 +62,8 @@ The boards support the following hardware features:
 +-----------+------------+-------------------------------------+
 | eMIOS     | on-chip    | pwm                                 |
 +-----------+------------+-------------------------------------+
+| QSPI      | on-chip    | flash                               |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not currently supported by the port.
 
@@ -172,6 +174,12 @@ EDMA
 The EDMA modules feature four EDMA3 instances: Instance 0 with 32 channels,
 and instances 1, 4, and 5, each with 16 channels.
 
+External Flash
+==============
+
+The on-board S26HS512T 512M-bit HyperFlash memory is connected to the QSPI controller
+port A1. This board configuration selects it as the default flash controller.
+
 Programming and Debugging
 *************************
 

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi

@@ -5,6 +5,7 @@
  */
 
 #include "s32z2xxdc2_s32z270_pinctrl.dtsi"
+#include <zephyr/dt-bindings/qspi/nxp-s32-qspi.h>
 
 &swt0 {
 	status = "okay";
@@ -58,3 +59,69 @@
 &sar_adc1 {
 	vref-mv = <1800>;
 };
+
+&qspi0 {
+	pinctrl-0 = <&qspi0_default>;
+	pinctrl-names = "default";
+	data-rate = "DDR";
+	column-space = <3>;
+	word-addressable;
+	hold-time-2x;
+	a-dll-freq-enable;
+	a-dll-ref-counter = <2>;
+	a-dll-resolution = <2>;
+	a-dll-coarse-delay = <2>;
+	a-dll-fine-delay = <2>;
+	a-dll-mode = "AUTO UPDATE";
+	a-rx-clock-source = "EXTERNAL DQS";
+	ahb-buffers-masters = <0 1 2 3>;
+	ahb-buffers-sizes = <256 256 256 256>;
+	ahb-buffers-all-masters;
+	status = "okay";
+
+	sfp_mdad {
+		compatible = "nxp,s32-qspi-sfp-mdad";
+
+		mdad_0: mdad_0 {
+			domain-id = <0>;
+			secure-attribute = <NXP_S32_QSPI_SECURE>;
+		};
+	};
+
+	sfp_frad {
+		compatible = "nxp,s32-qspi-sfp-frad";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		frad_0: frad@0 {
+			reg = <0x0 DT_SIZE_M(512)>;
+			master-domain-acp-policy = <NXP_S32_QSPI_SECURE>;
+		};
+	};
+
+	s26hs512t: s26hs512t@0 {
+		compatible = "nxp,s32-qspi-hyperflash";
+		reg = <0>;
+		jedec-id = [00 34 00 7b 00 1a 00 0f 00 90];
+		device-id-word-addr = <0x800>;
+		size = <DT_SIZE_M(512)>;
+		write-block-size = <2>;
+		read-latency-cycles = <16>;
+		max-program-buffer-size = <256>;
+		vcc-mv = <1800>;
+		drive-strength-ohm = <27>;
+		ppw-sectors-addr-mapping = "LOW";
+		status = "okay";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			storage_partition: partition@0 {
+				label = "storage";
+				reg = <0x0 0x10000>;
+			};
+		};
+	};
+};

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi

@@ -127,4 +127,25 @@
 			drive-open-drain;
 		};
 	};
+
+	qspi0_default: qspi0_default {
+		group1 {
+			pinmux = <PI4_QSPI_0_DATA_A_O0>, <PH14_QSPI_0_DATA_A_O1>,
+				 <PI8_QSPI_0_DATA_A_O2>, <PI1_QSPI_0_DATA_A_O3>,
+				 <PI5_QSPI_0_DATA_A_O4>, <PH15_QSPI_0_DATA_A_O5>,
+				 <PI7_QSPI_0_DATA_A_O6>, <PI0_QSPI_0_DATA_A_O7>,
+				 <PI6_QSPI_0_DQS_A_O>;
+			output-enable;
+			input-enable;
+		};
+		group2 {
+			pinmux = <PH13_QSPI_0_CS_A0>, <PI9_QSPI_0_CS_A1>,
+				 <PI2_QSPI_0_CK_A_B>, <PI3_QSPI_0_CK_A>;
+			output-enable;
+		};
+		group3 {
+			pinmux = <PH12_QSPI_0_INTA_B>;
+			input-enable;
+		};
+	};
 };

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts

@@ -16,6 +16,7 @@
 		zephyr,sram = &dram0;
 		zephyr,flash = &cram0;
 		zephyr,canbus = &canxl0;
+		zephyr,flash-controller = &s26hs512t;
 	};
 
 	aliases {

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts

@@ -16,6 +16,7 @@
 		zephyr,sram = &dram1;
 		zephyr,flash = &cram1;
 		zephyr,canbus = &flexcan0;
+		zephyr,flash-controller = &s26hs512t;
 	};
 
 	aliases {

dts/arm/nxp/nxp_s32z27x_r52.dtsi

@@ -1431,5 +1431,21 @@
 				status = "disabled";
 			};
 		};
+
+		qspi0: qspi@42320000 {
+			compatible = "nxp,s32-qspi";
+			reg = <0x42320000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		qspi1: qspi@42340000 {
+			compatible = "nxp,s32-qspi";
+			reg = <0x42340000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 	};
 };