drivers: i2s_mcux_sai: Clang format
Clang format to fix strange formatting, shortens the line count by 100 Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
Declan Snyder
Alberto Escolar
parent
bb24c83d70
commit
41580bdc07
1 changed files with 200 additions and 305 deletions
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@ -110,14 +110,11 @@ struct i2s_dev_data {
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void *rx_out_msgs[CONFIG_I2S_RX_BLOCK_COUNT];
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};
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static void i2s_dma_tx_callback(const struct device *, void *,
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uint32_t, int);
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static void i2s_dma_tx_callback(const struct device *, void *, uint32_t, int);
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static void i2s_tx_stream_disable(const struct device *, bool drop);
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static void i2s_rx_stream_disable(const struct device *,
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bool in_drop, bool out_drop);
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static void i2s_rx_stream_disable(const struct device *, bool in_drop, bool out_drop);
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static inline void i2s_purge_stream_buffers(struct stream *strm,
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struct k_mem_slab *mem_slab,
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static inline void i2s_purge_stream_buffers(struct stream *strm, struct k_mem_slab *mem_slab,
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bool in_drop, bool out_drop)
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{
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void *buffer;
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@ -145,8 +142,7 @@ static void i2s_tx_stream_disable(const struct device *dev, bool drop)
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LOG_DBG("Stopping DMA channel %u for TX stream", strm->dma_channel);
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/* Disable FIFO DMA request */
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SAI_TxEnableDMA(dev_cfg->base, kSAI_FIFORequestDMAEnable,
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false);
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SAI_TxEnableDMA(dev_cfg->base, kSAI_FIFORequestDMAEnable, false);
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dma_stop(dev_dma, strm->dma_channel);
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@ -163,20 +159,17 @@ static void i2s_tx_stream_disable(const struct device *dev, bool drop)
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/* If Tx is disabled, reset the FIFO pointer, clear error flags */
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if ((dev_cfg->base->TCSR & I2S_TCSR_TE_MASK) == 0UL) {
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dev_cfg->base->TCSR |=
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(I2S_TCSR_FR_MASK | I2S_TCSR_SR_MASK);
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dev_cfg->base->TCSR |= (I2S_TCSR_FR_MASK | I2S_TCSR_SR_MASK);
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dev_cfg->base->TCSR &= ~I2S_TCSR_SR_MASK;
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}
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/* purge buffers queued in the stream */
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if (drop) {
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i2s_purge_stream_buffers(strm, dev_data->tx.cfg.mem_slab,
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true, true);
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i2s_purge_stream_buffers(strm, dev_data->tx.cfg.mem_slab, true, true);
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}
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}
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static void i2s_rx_stream_disable(const struct device *dev,
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bool in_drop, bool out_drop)
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static void i2s_rx_stream_disable(const struct device *dev, bool in_drop, bool out_drop)
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{
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struct i2s_dev_data *dev_data = dev->data;
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struct stream *strm = &dev_data->rx;
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@ -190,8 +183,7 @@ static void i2s_rx_stream_disable(const struct device *dev,
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dev_cfg->base->RCR3 &= ~I2S_RCR3_RCE_MASK;
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/* Disable DMA enable bit */
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SAI_RxEnableDMA(dev_cfg->base, kSAI_FIFORequestDMAEnable,
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false);
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SAI_RxEnableDMA(dev_cfg->base, kSAI_FIFORequestDMAEnable, false);
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/* Disable Rx */
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SAI_RxEnable(dev_cfg->base, false);
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@ -206,13 +198,11 @@ static void i2s_rx_stream_disable(const struct device *dev,
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/* purge buffers queued in the stream */
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if (in_drop || out_drop) {
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i2s_purge_stream_buffers(strm, dev_data->rx.cfg.mem_slab,
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in_drop, out_drop);
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i2s_purge_stream_buffers(strm, dev_data->rx.cfg.mem_slab, in_drop, out_drop);
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}
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}
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static int i2s_tx_reload_multiple_dma_blocks(const struct device *dev,
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uint8_t *blocks_queued)
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static int i2s_tx_reload_multiple_dma_blocks(const struct device *dev, uint8_t *blocks_queued)
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{
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struct i2s_dev_data *dev_data = dev->data;
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const struct i2s_mcux_config *dev_cfg = dev->config;
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@ -237,10 +227,8 @@ static int i2s_tx_reload_multiple_dma_blocks(const struct device *dev,
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}
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/* reload the DMA */
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ret = dma_reload(dev_data->dev_dma, strm->dma_channel,
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(uint32_t)buffer,
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(uint32_t)&base->TDR[strm->start_channel],
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strm->cfg.block_size);
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ret = dma_reload(dev_data->dev_dma, strm->dma_channel, (uint32_t)buffer,
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(uint32_t)&base->TDR[strm->start_channel], strm->cfg.block_size);
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if (ret != 0) {
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LOG_ERR("dma_reload() failed with error 0x%x", ret);
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break;
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@ -248,11 +236,9 @@ static int i2s_tx_reload_multiple_dma_blocks(const struct device *dev,
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(strm->free_tx_dma_blocks)--;
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ret = k_msgq_put(&strm->out_queue,
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&buffer, K_NO_WAIT);
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ret = k_msgq_put(&strm->out_queue, &buffer, K_NO_WAIT);
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if (ret != 0) {
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LOG_ERR("buffer %p -> out %p err %d",
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buffer, &strm->out_queue, ret);
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LOG_ERR("buffer %p -> out %p err %d", buffer, &strm->out_queue, ret);
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break;
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}
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@ -264,8 +250,8 @@ static int i2s_tx_reload_multiple_dma_blocks(const struct device *dev,
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}
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/* This function is executed in the interrupt context */
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static void i2s_dma_tx_callback(const struct device *dma_dev,
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void *arg, uint32_t channel, int status)
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static void i2s_dma_tx_callback(const struct device *dma_dev, void *arg, uint32_t channel,
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int status)
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{
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const struct device *dev = (struct device *)arg;
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struct i2s_dev_data *dev_data = dev->data;
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@ -287,8 +273,7 @@ static void i2s_dma_tx_callback(const struct device *dma_dev,
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if (strm->free_tx_dma_blocks > MAX_TX_DMA_BLOCKS) {
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strm->state = I2S_STATE_ERROR;
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LOG_ERR("free_tx_dma_blocks exceeded maximum, now %d",
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strm->free_tx_dma_blocks);
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LOG_ERR("free_tx_dma_blocks exceeded maximum, now %d", strm->free_tx_dma_blocks);
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goto disabled_exit_no_drop;
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}
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@ -316,8 +301,7 @@ static void i2s_dma_tx_callback(const struct device *dma_dev,
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}
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dma_start(dev_data->dev_dma, strm->dma_channel);
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if (blocks_queued ||
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(strm->free_tx_dma_blocks < MAX_TX_DMA_BLOCKS)) {
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if (blocks_queued || (strm->free_tx_dma_blocks < MAX_TX_DMA_BLOCKS)) {
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goto enabled_exit;
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} else {
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/* all DMA blocks are free but no blocks were queued */
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@ -349,8 +333,8 @@ enabled_exit:
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return;
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}
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static void i2s_dma_rx_callback(const struct device *dma_dev,
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void *arg, uint32_t channel, int status)
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static void i2s_dma_rx_callback(const struct device *dma_dev, void *arg, uint32_t channel,
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int status)
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{
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struct device *dev = (struct device *)arg;
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const struct i2s_mcux_config *dev_cfg = dev->config;
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@ -372,50 +356,40 @@ static void i2s_dma_rx_callback(const struct device *dma_dev,
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/* put buffer to output queue */
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ret = k_msgq_put(&strm->out_queue, &buffer, K_NO_WAIT);
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if (ret != 0) {
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LOG_ERR("buffer %p -> out_queue %p err %d",
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buffer,
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&strm->out_queue, ret);
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LOG_ERR("buffer %p -> out_queue %p err %d", buffer, &strm->out_queue, ret);
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i2s_rx_stream_disable(dev, false, false);
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strm->state = I2S_STATE_ERROR;
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return;
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}
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if (strm->state == I2S_STATE_RUNNING) {
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/* allocate new buffer for next audio frame */
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ret = k_mem_slab_alloc(strm->cfg.mem_slab,
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&buffer, K_NO_WAIT);
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ret = k_mem_slab_alloc(strm->cfg.mem_slab, &buffer, K_NO_WAIT);
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if (ret != 0) {
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LOG_ERR("buffer alloc from slab %p err %d",
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strm->cfg.mem_slab, ret);
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LOG_ERR("buffer alloc from slab %p err %d", strm->cfg.mem_slab,
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ret);
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i2s_rx_stream_disable(dev, false, false);
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strm->state = I2S_STATE_ERROR;
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} else {
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uint32_t data_path = strm->start_channel;
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ret = dma_reload(dev_data->dev_dma,
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strm->dma_channel,
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(uint32_t)&base->RDR[data_path],
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(uint32_t)buffer,
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ret = dma_reload(dev_data->dev_dma, strm->dma_channel,
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(uint32_t)&base->RDR[data_path], (uint32_t)buffer,
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strm->cfg.block_size);
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if (ret != 0) {
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LOG_ERR("dma_reload() failed with error 0x%x",
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ret);
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i2s_rx_stream_disable(dev,
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false, false);
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LOG_ERR("dma_reload() failed with error 0x%x", ret);
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i2s_rx_stream_disable(dev, false, false);
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strm->state = I2S_STATE_ERROR;
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return;
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}
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/* put buffer in input queue */
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ret = k_msgq_put(&strm->in_queue,
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&buffer, K_NO_WAIT);
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ret = k_msgq_put(&strm->in_queue, &buffer, K_NO_WAIT);
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if (ret != 0) {
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LOG_ERR("%p -> in_queue %p err %d",
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buffer, &strm->in_queue,
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LOG_ERR("%p -> in_queue %p err %d", buffer, &strm->in_queue,
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ret);
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}
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dma_start(dev_data->dev_dma,
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strm->dma_channel);
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dma_start(dev_data->dev_dma, strm->dma_channel);
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}
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} else {
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i2s_rx_stream_disable(dev, true, false);
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@ -434,15 +408,13 @@ static void enable_mclk_direction(const struct device *dev, bool dir)
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const struct i2s_mcux_config *dev_cfg = dev->config;
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uint32_t offset = dev_cfg->mclk_pin_offset;
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uint32_t mask = dev_cfg->mclk_pin_mask;
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uint32_t *gpr = (uint32_t *)
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(DT_REG_ADDR(DT_NODELABEL(iomuxcgpr)) + offset);
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uint32_t *gpr = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(iomuxcgpr)) + offset);
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if (dir) {
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*gpr |= mask;
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} else {
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*gpr &= ~mask;
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}
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}
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static void get_mclk_rate(const struct device *dev, uint32_t *mclk)
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@ -478,9 +450,7 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
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(dev_data->tx.state != I2S_STATE_READY) &&
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(dev_data->rx.state != I2S_STATE_NOT_READY) &&
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(dev_data->rx.state != I2S_STATE_READY)) {
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LOG_ERR("invalid state tx(%u) rx(%u)",
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dev_data->tx.state,
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dev_data->rx.state);
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LOG_ERR("invalid state tx(%u) rx(%u)", dev_data->tx.state, dev_data->rx.state);
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if (dir == I2S_DIR_TX) {
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dev_data->tx.state = I2S_STATE_NOT_READY;
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} else {
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@ -490,8 +460,7 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
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}
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if (i2s_cfg->frame_clk_freq == 0U) {
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LOG_ERR("Invalid frame_clk_freq %u",
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i2s_cfg->frame_clk_freq);
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LOG_ERR("Invalid frame_clk_freq %u", i2s_cfg->frame_clk_freq);
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if (dir == I2S_DIR_TX) {
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dev_data->tx.state = I2S_STATE_NOT_READY;
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} else {
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@ -500,8 +469,7 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
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return 0;
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}
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if (word_size_bits < SAI_WORD_SIZE_BITS_MIN ||
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word_size_bits > SAI_WORD_SIZE_BITS_MAX) {
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if (word_size_bits < SAI_WORD_SIZE_BITS_MIN || word_size_bits > SAI_WORD_SIZE_BITS_MAX) {
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LOG_ERR("Unsupported I2S word size %u", word_size_bits);
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if (dir == I2S_DIR_TX) {
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dev_data->tx.state = I2S_STATE_NOT_READY;
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@ -511,8 +479,7 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
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return -EINVAL;
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}
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if (num_words < SAI_WORD_PER_FRAME_MIN ||
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num_words > SAI_WORD_PER_FRAME_MAX) {
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if (num_words < SAI_WORD_PER_FRAME_MIN || num_words > SAI_WORD_PER_FRAME_MAX) {
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LOG_ERR("Unsupported words length %u", num_words);
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if (dir == I2S_DIR_TX) {
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dev_data->tx.state = I2S_STATE_NOT_READY;
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@ -550,14 +517,12 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
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config.bitClock.bclkInputDelay = false;
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/* frame sync default configurations */
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#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && \
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FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
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#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
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config.frameSync.frameSyncGenerateOnDemand = false;
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#endif
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/* serial data default configurations */
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#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && \
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FSL_FEATURE_SAI_HAS_CHANNEL_MODE
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#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE
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config.serialData.dataMode = kSAI_DataPinStateOutputZero;
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#endif
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@ -566,18 +531,14 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
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/* format */
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switch (i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) {
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case I2S_FMT_DATA_FORMAT_I2S:
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SAI_GetClassicI2SConfig(&config, word_size_bits,
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kSAI_Stereo,
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dev_cfg->tx_channel);
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SAI_GetClassicI2SConfig(&config, word_size_bits, kSAI_Stereo, dev_cfg->tx_channel);
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break;
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case I2S_FMT_DATA_FORMAT_LEFT_JUSTIFIED:
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SAI_GetLeftJustifiedConfig(&config, word_size_bits,
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kSAI_Stereo,
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SAI_GetLeftJustifiedConfig(&config, word_size_bits, kSAI_Stereo,
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dev_cfg->tx_channel);
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break;
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case I2S_FMT_DATA_FORMAT_PCM_SHORT:
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SAI_GetDSPConfig(&config, kSAI_FrameSyncLenOneBitClk,
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word_size_bits, kSAI_Stereo,
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SAI_GetDSPConfig(&config, kSAI_FrameSyncLenOneBitClk, word_size_bits, kSAI_Stereo,
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dev_cfg->tx_channel);
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/* We need to set the data word count manually, since the HAL
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* function does not
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@ -587,8 +548,7 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
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config.bitClock.bclkPolarity = kSAI_SampleOnFallingEdge;
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break;
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case I2S_FMT_DATA_FORMAT_PCM_LONG:
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SAI_GetTDMConfig(&config, kSAI_FrameSyncLenPerWordWidth,
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word_size_bits, num_words,
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SAI_GetTDMConfig(&config, kSAI_FrameSyncLenPerWordWidth, word_size_bits, num_words,
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dev_cfg->tx_channel);
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config.bitClock.bclkPolarity = kSAI_SampleOnFallingEdge;
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break;
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@ -623,13 +583,11 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
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if (i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE) {
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config.masterSlave = kSAI_Slave;
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} else {
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config.masterSlave =
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kSAI_Bclk_Master_FrameSync_Slave;
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config.masterSlave = kSAI_Bclk_Master_FrameSync_Slave;
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}
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} else {
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if (i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE) {
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config.masterSlave =
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kSAI_Bclk_Slave_FrameSync_Master;
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config.masterSlave = kSAI_Bclk_Slave_FrameSync_Master;
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} else {
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config.masterSlave = kSAI_Master;
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}
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@ -644,66 +602,57 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
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case I2S_FMT_CLK_NF_IB:
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/* Swap bclk polarity */
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config.bitClock.bclkPolarity =
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(config.bitClock.bclkPolarity == kSAI_SampleOnFallingEdge) ?
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kSAI_SampleOnRisingEdge :
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kSAI_SampleOnFallingEdge;
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(config.bitClock.bclkPolarity == kSAI_SampleOnFallingEdge)
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? kSAI_SampleOnRisingEdge
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: kSAI_SampleOnFallingEdge;
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break;
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case I2S_FMT_CLK_IF_NB:
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/* Swap frame sync polarity */
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config.frameSync.frameSyncPolarity =
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(config.frameSync.frameSyncPolarity == kSAI_PolarityActiveHigh) ?
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kSAI_PolarityActiveLow :
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kSAI_PolarityActiveHigh;
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(config.frameSync.frameSyncPolarity == kSAI_PolarityActiveHigh)
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? kSAI_PolarityActiveLow
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: kSAI_PolarityActiveHigh;
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break;
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case I2S_FMT_CLK_IF_IB:
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/* Swap frame sync and bclk polarity */
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config.frameSync.frameSyncPolarity =
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(config.frameSync.frameSyncPolarity == kSAI_PolarityActiveHigh) ?
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kSAI_PolarityActiveLow :
|
||||
kSAI_PolarityActiveHigh;
|
||||
(config.frameSync.frameSyncPolarity == kSAI_PolarityActiveHigh)
|
||||
? kSAI_PolarityActiveLow
|
||||
: kSAI_PolarityActiveHigh;
|
||||
config.bitClock.bclkPolarity =
|
||||
(config.bitClock.bclkPolarity == kSAI_SampleOnFallingEdge) ?
|
||||
kSAI_SampleOnRisingEdge :
|
||||
kSAI_SampleOnFallingEdge;
|
||||
(config.bitClock.bclkPolarity == kSAI_SampleOnFallingEdge)
|
||||
? kSAI_SampleOnRisingEdge
|
||||
: kSAI_SampleOnFallingEdge;
|
||||
break;
|
||||
}
|
||||
|
||||
/* PCM short format always requires that WS be one BCLK cycle */
|
||||
if ((i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) !=
|
||||
I2S_FMT_DATA_FORMAT_PCM_SHORT) {
|
||||
if ((i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) != I2S_FMT_DATA_FORMAT_PCM_SHORT) {
|
||||
config.frameSync.frameSyncWidth = (uint8_t)word_size_bits;
|
||||
}
|
||||
|
||||
if (dir == I2S_DIR_TX) {
|
||||
memcpy(&dev_data->tx.cfg, i2s_cfg, sizeof(struct i2s_config));
|
||||
LOG_DBG("tx slab free_list = 0x%x",
|
||||
(uint32_t)i2s_cfg->mem_slab->free_list);
|
||||
LOG_DBG("tx slab num_blocks = %d",
|
||||
(uint32_t)i2s_cfg->mem_slab->info.num_blocks);
|
||||
LOG_DBG("tx slab block_size = %d",
|
||||
(uint32_t)i2s_cfg->mem_slab->info.block_size);
|
||||
LOG_DBG("tx slab buffer = 0x%x",
|
||||
(uint32_t)i2s_cfg->mem_slab->buffer);
|
||||
LOG_DBG("tx slab free_list = 0x%x", (uint32_t)i2s_cfg->mem_slab->free_list);
|
||||
LOG_DBG("tx slab num_blocks = %d", (uint32_t)i2s_cfg->mem_slab->info.num_blocks);
|
||||
LOG_DBG("tx slab block_size = %d", (uint32_t)i2s_cfg->mem_slab->info.block_size);
|
||||
LOG_DBG("tx slab buffer = 0x%x", (uint32_t)i2s_cfg->mem_slab->buffer);
|
||||
|
||||
/* set bit clock divider */
|
||||
SAI_TxSetConfig(base, &config);
|
||||
dev_data->tx.start_channel = config.startChannel;
|
||||
/* Disable the channel FIFO */
|
||||
base->TCR3 &= ~I2S_TCR3_TCE_MASK;
|
||||
SAI_TxSetBitClockRate(base, mclk,
|
||||
i2s_cfg->frame_clk_freq,
|
||||
word_size_bits,
|
||||
SAI_TxSetBitClockRate(base, mclk, i2s_cfg->frame_clk_freq, word_size_bits,
|
||||
i2s_cfg->channels);
|
||||
LOG_DBG("tx start_channel = %d", dev_data->tx.start_channel);
|
||||
/*set up dma settings*/
|
||||
dev_data->tx.dma_cfg.source_data_size = word_size_bits / 8;
|
||||
dev_data->tx.dma_cfg.dest_data_size = word_size_bits / 8;
|
||||
dev_data->tx.dma_cfg.source_burst_length =
|
||||
i2s_cfg->word_size / 8;
|
||||
dev_data->tx.dma_cfg.dest_burst_length =
|
||||
i2s_cfg->word_size / 8;
|
||||
dev_data->tx.dma_cfg.source_burst_length = i2s_cfg->word_size / 8;
|
||||
dev_data->tx.dma_cfg.dest_burst_length = i2s_cfg->word_size / 8;
|
||||
dev_data->tx.dma_cfg.user_data = (void *)dev;
|
||||
dev_data->tx.state = I2S_STATE_READY;
|
||||
} else {
|
||||
|
|
@ -711,30 +660,22 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
|
|||
config.fifo.fifoWatermark = 0;
|
||||
|
||||
memcpy(&dev_data->rx.cfg, i2s_cfg, sizeof(struct i2s_config));
|
||||
LOG_DBG("rx slab free_list = 0x%x",
|
||||
(uint32_t)i2s_cfg->mem_slab->free_list);
|
||||
LOG_DBG("rx slab num_blocks = %d",
|
||||
(uint32_t)i2s_cfg->mem_slab->info.num_blocks);
|
||||
LOG_DBG("rx slab block_size = %d",
|
||||
(uint32_t)i2s_cfg->mem_slab->info.block_size);
|
||||
LOG_DBG("rx slab buffer = 0x%x",
|
||||
(uint32_t)i2s_cfg->mem_slab->buffer);
|
||||
LOG_DBG("rx slab free_list = 0x%x", (uint32_t)i2s_cfg->mem_slab->free_list);
|
||||
LOG_DBG("rx slab num_blocks = %d", (uint32_t)i2s_cfg->mem_slab->info.num_blocks);
|
||||
LOG_DBG("rx slab block_size = %d", (uint32_t)i2s_cfg->mem_slab->info.block_size);
|
||||
LOG_DBG("rx slab buffer = 0x%x", (uint32_t)i2s_cfg->mem_slab->buffer);
|
||||
|
||||
/* set bit clock divider */
|
||||
SAI_RxSetConfig(base, &config);
|
||||
dev_data->rx.start_channel = config.startChannel;
|
||||
SAI_RxSetBitClockRate(base, mclk,
|
||||
i2s_cfg->frame_clk_freq,
|
||||
word_size_bits,
|
||||
SAI_RxSetBitClockRate(base, mclk, i2s_cfg->frame_clk_freq, word_size_bits,
|
||||
i2s_cfg->channels);
|
||||
LOG_DBG("rx start_channel = %d", dev_data->rx.start_channel);
|
||||
/*set up dma settings*/
|
||||
dev_data->rx.dma_cfg.source_data_size = word_size_bits / 8;
|
||||
dev_data->rx.dma_cfg.dest_data_size = word_size_bits / 8;
|
||||
dev_data->rx.dma_cfg.source_burst_length =
|
||||
i2s_cfg->word_size / 8;
|
||||
dev_data->rx.dma_cfg.dest_burst_length =
|
||||
i2s_cfg->word_size / 8;
|
||||
dev_data->rx.dma_cfg.source_burst_length = i2s_cfg->word_size / 8;
|
||||
dev_data->rx.dma_cfg.dest_burst_length = i2s_cfg->word_size / 8;
|
||||
dev_data->rx.dma_cfg.user_data = (void *)dev;
|
||||
dev_data->rx.state = I2S_STATE_READY;
|
||||
}
|
||||
|
|
@ -742,8 +683,7 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
|
|||
return 0;
|
||||
}
|
||||
|
||||
const struct i2s_config *i2s_mcux_config_get(const struct device *dev,
|
||||
enum i2s_dir dir)
|
||||
const struct i2s_config *i2s_mcux_config_get(const struct device *dev, enum i2s_dir dir)
|
||||
{
|
||||
struct i2s_dev_data *dev_data = dev->data;
|
||||
|
||||
|
|
@ -793,7 +733,6 @@ static int i2s_tx_stream_start(const struct device *dev)
|
|||
strm->dma_cfg.head_block = &strm->dma_block;
|
||||
strm->dma_cfg.user_data = (void *)dev;
|
||||
|
||||
|
||||
(strm->free_tx_dma_blocks)--;
|
||||
dma_config(dev_dma, strm->dma_channel, &strm->dma_cfg);
|
||||
|
||||
|
|
@ -852,8 +791,7 @@ static int i2s_rx_stream_start(const struct device *dev)
|
|||
}
|
||||
|
||||
/* allocate 1st receive buffer from SLAB */
|
||||
ret = k_mem_slab_alloc(strm->cfg.mem_slab, &buffer,
|
||||
K_NO_WAIT);
|
||||
ret = k_mem_slab_alloc(strm->cfg.mem_slab, &buffer, K_NO_WAIT);
|
||||
if (ret != 0) {
|
||||
LOG_DBG("buffer alloc from mem_slab failed (%d)", ret);
|
||||
return ret;
|
||||
|
|
@ -889,15 +827,13 @@ static int i2s_rx_stream_start(const struct device *dev)
|
|||
for (int i = 0; i < NUM_DMA_BLOCKS_RX_PREP - 1; i++) {
|
||||
|
||||
/* allocate receive buffer from SLAB */
|
||||
ret = k_mem_slab_alloc(strm->cfg.mem_slab, &buffer,
|
||||
K_NO_WAIT);
|
||||
ret = k_mem_slab_alloc(strm->cfg.mem_slab, &buffer, K_NO_WAIT);
|
||||
if (ret != 0) {
|
||||
LOG_ERR("buffer alloc from mem_slab failed (%d)", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dma_reload(dev_dma, strm->dma_channel,
|
||||
(uint32_t)&base->RDR[data_path],
|
||||
ret = dma_reload(dev_dma, strm->dma_channel, (uint32_t)&base->RDR[data_path],
|
||||
(uint32_t)buffer, blk_cfg->block_size);
|
||||
if (ret != 0) {
|
||||
LOG_ERR("dma_reload() failed with error 0x%x", ret);
|
||||
|
|
@ -907,8 +843,7 @@ static int i2s_rx_stream_start(const struct device *dev)
|
|||
/* put buffer in input queue */
|
||||
ret = k_msgq_put(&strm->in_queue, &buffer, K_NO_WAIT);
|
||||
if (ret != 0) {
|
||||
LOG_ERR("failed to put buffer in input queue, ret2 %d",
|
||||
ret);
|
||||
LOG_ERR("failed to put buffer in input queue, ret2 %d", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
|
@ -916,8 +851,7 @@ static int i2s_rx_stream_start(const struct device *dev)
|
|||
LOG_DBG("Starting DMA Ch%u", strm->dma_channel);
|
||||
ret = dma_start(dev_dma, strm->dma_channel);
|
||||
if (ret < 0) {
|
||||
LOG_ERR("Failed to start DMA Ch%d (%d)", strm->dma_channel,
|
||||
ret);
|
||||
LOG_ERR("Failed to start DMA Ch%d (%d)", strm->dma_channel, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -933,8 +867,7 @@ static int i2s_rx_stream_start(const struct device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int i2s_mcux_trigger(const struct device *dev, enum i2s_dir dir,
|
||||
enum i2s_trigger_cmd cmd)
|
||||
static int i2s_mcux_trigger(const struct device *dev, enum i2s_dir dir, enum i2s_trigger_cmd cmd)
|
||||
{
|
||||
struct i2s_dev_data *dev_data = dev->data;
|
||||
struct stream *strm;
|
||||
|
|
@ -951,8 +884,7 @@ static int i2s_mcux_trigger(const struct device *dev, enum i2s_dir dir,
|
|||
switch (cmd) {
|
||||
case I2S_TRIGGER_START:
|
||||
if (strm->state != I2S_STATE_READY) {
|
||||
LOG_ERR("START trigger: invalid state %u",
|
||||
strm->state);
|
||||
LOG_ERR("START trigger: invalid state %u", strm->state);
|
||||
ret = -EIO;
|
||||
break;
|
||||
}
|
||||
|
|
@ -975,8 +907,7 @@ static int i2s_mcux_trigger(const struct device *dev, enum i2s_dir dir,
|
|||
|
||||
case I2S_TRIGGER_DROP:
|
||||
if (strm->state == I2S_STATE_NOT_READY) {
|
||||
LOG_ERR("DROP trigger: invalid state %d",
|
||||
strm->state);
|
||||
LOG_ERR("DROP trigger: invalid state %d", strm->state);
|
||||
ret = -EIO;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1002,8 +933,7 @@ static int i2s_mcux_trigger(const struct device *dev, enum i2s_dir dir,
|
|||
|
||||
case I2S_TRIGGER_DRAIN:
|
||||
if (strm->state != I2S_STATE_RUNNING) {
|
||||
LOG_ERR("DRAIN/STOP trigger: invalid state %d",
|
||||
strm->state);
|
||||
LOG_ERR("DRAIN/STOP trigger: invalid state %d", strm->state);
|
||||
ret = -EIO;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1013,8 +943,7 @@ static int i2s_mcux_trigger(const struct device *dev, enum i2s_dir dir,
|
|||
|
||||
case I2S_TRIGGER_PREPARE:
|
||||
if (strm->state != I2S_STATE_ERROR) {
|
||||
LOG_ERR("PREPARE trigger: invalid state %d",
|
||||
strm->state);
|
||||
LOG_ERR("PREPARE trigger: invalid state %d", strm->state);
|
||||
ret = -EIO;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1035,8 +964,7 @@ static int i2s_mcux_trigger(const struct device *dev, enum i2s_dir dir,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int i2s_mcux_read(const struct device *dev, void **mem_block,
|
||||
size_t *size)
|
||||
static int i2s_mcux_read(const struct device *dev, void **mem_block, size_t *size)
|
||||
{
|
||||
struct i2s_dev_data *dev_data = dev->data;
|
||||
struct stream *strm = &dev_data->rx;
|
||||
|
|
@ -1049,8 +977,7 @@ static int i2s_mcux_read(const struct device *dev, void **mem_block,
|
|||
return -EIO;
|
||||
}
|
||||
|
||||
status = k_msgq_get(&strm->out_queue, &buffer,
|
||||
SYS_TIMEOUT_MS(strm->cfg.timeout));
|
||||
status = k_msgq_get(&strm->out_queue, &buffer, SYS_TIMEOUT_MS(strm->cfg.timeout));
|
||||
if (status != 0) {
|
||||
if (strm->state == I2S_STATE_ERROR) {
|
||||
ret = -EIO;
|
||||
|
|
@ -1066,22 +993,19 @@ static int i2s_mcux_read(const struct device *dev, void **mem_block,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int i2s_mcux_write(const struct device *dev, void *mem_block,
|
||||
size_t size)
|
||||
static int i2s_mcux_write(const struct device *dev, void *mem_block, size_t size)
|
||||
{
|
||||
struct i2s_dev_data *dev_data = dev->data;
|
||||
struct stream *strm = &dev_data->tx;
|
||||
int ret;
|
||||
|
||||
LOG_DBG("i2s_mcux_write");
|
||||
if (strm->state != I2S_STATE_RUNNING &&
|
||||
strm->state != I2S_STATE_READY) {
|
||||
if (strm->state != I2S_STATE_RUNNING && strm->state != I2S_STATE_READY) {
|
||||
LOG_ERR("invalid state (%d)", strm->state);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
ret = k_msgq_put(&strm->in_queue, &mem_block,
|
||||
SYS_TIMEOUT_MS(strm->cfg.timeout));
|
||||
ret = k_msgq_put(&strm->in_queue, &mem_block, SYS_TIMEOUT_MS(strm->cfg.timeout));
|
||||
if (ret) {
|
||||
LOG_DBG("k_msgq_put returned code %d", ret);
|
||||
return ret;
|
||||
|
|
@ -1147,8 +1071,8 @@ static void audio_clock_settings(const struct device *dev)
|
|||
uint32_t clock_name = (uint32_t)dev_cfg->clk_sub_sys;
|
||||
|
||||
/*Clock setting for SAI*/
|
||||
imxrt_audio_codec_pll_init(clock_name, dev_cfg->clk_src,
|
||||
dev_cfg->clk_pre_div, dev_cfg->clk_src_div);
|
||||
imxrt_audio_codec_pll_init(clock_name, dev_cfg->clk_src, dev_cfg->clk_pre_div,
|
||||
dev_cfg->clk_src_div);
|
||||
|
||||
#ifdef CONFIG_SOC_SERIES_IMXRT11XX
|
||||
audioPllConfig.loopDivider = dev_cfg->pll_lp;
|
||||
|
|
@ -1183,14 +1107,14 @@ static int i2s_mcux_initialize(const struct device *dev)
|
|||
}
|
||||
|
||||
/* Initialize the buffer queues */
|
||||
k_msgq_init(&dev_data->tx.in_queue, (char *)dev_data->tx_in_msgs,
|
||||
sizeof(void *), CONFIG_I2S_TX_BLOCK_COUNT);
|
||||
k_msgq_init(&dev_data->rx.in_queue, (char *)dev_data->rx_in_msgs,
|
||||
sizeof(void *), CONFIG_I2S_RX_BLOCK_COUNT);
|
||||
k_msgq_init(&dev_data->tx.out_queue, (char *)dev_data->tx_out_msgs,
|
||||
sizeof(void *), CONFIG_I2S_TX_BLOCK_COUNT);
|
||||
k_msgq_init(&dev_data->rx.out_queue, (char *)dev_data->rx_out_msgs,
|
||||
sizeof(void *), CONFIG_I2S_RX_BLOCK_COUNT);
|
||||
k_msgq_init(&dev_data->tx.in_queue, (char *)dev_data->tx_in_msgs, sizeof(void *),
|
||||
CONFIG_I2S_TX_BLOCK_COUNT);
|
||||
k_msgq_init(&dev_data->rx.in_queue, (char *)dev_data->rx_in_msgs, sizeof(void *),
|
||||
CONFIG_I2S_RX_BLOCK_COUNT);
|
||||
k_msgq_init(&dev_data->tx.out_queue, (char *)dev_data->tx_out_msgs, sizeof(void *),
|
||||
CONFIG_I2S_TX_BLOCK_COUNT);
|
||||
k_msgq_init(&dev_data->rx.out_queue, (char *)dev_data->rx_out_msgs, sizeof(void *),
|
||||
CONFIG_I2S_RX_BLOCK_COUNT);
|
||||
|
||||
/* register ISR */
|
||||
dev_cfg->irq_connect(dev);
|
||||
|
|
@ -1210,13 +1134,11 @@ static int i2s_mcux_initialize(const struct device *dev)
|
|||
dev_data->rx.state = I2S_STATE_NOT_READY;
|
||||
|
||||
#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
|
||||
(defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && \
|
||||
(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
|
||||
(defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
|
||||
sai_master_clock_t mclkConfig = {
|
||||
#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
|
||||
.mclkOutputEnable = true,
|
||||
#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && \
|
||||
(FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
|
||||
#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
|
||||
.mclkSource = kSAI_MclkSourceSysclk,
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -1226,10 +1148,8 @@ static int i2s_mcux_initialize(const struct device *dev)
|
|||
get_mclk_rate(dev, &mclk);
|
||||
/* master clock configurations */
|
||||
#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
|
||||
(defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && \
|
||||
(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
|
||||
#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && \
|
||||
(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
|
||||
(defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
|
||||
#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
|
||||
mclkConfig.mclkHz = mclk;
|
||||
mclkConfig.mclkSourceClkHz = mclk;
|
||||
#endif
|
||||
|
|
@ -1259,94 +1179,69 @@ static const struct i2s_driver_api i2s_mcux_driver_api = {
|
|||
.clk_src = DT_INST_PROP(i2s_id, clock_mux), \
|
||||
.clk_pre_div = DT_INST_PROP(i2s_id, pre_div), \
|
||||
.clk_src_div = DT_INST_PROP(i2s_id, podf), \
|
||||
.pll_src = \
|
||||
DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
|
||||
pll_clocks, src, value), \
|
||||
.pll_lp = \
|
||||
DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
|
||||
pll_clocks, lp, value), \
|
||||
.pll_pd = \
|
||||
DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
|
||||
pll_clocks, pd, value), \
|
||||
.pll_num = \
|
||||
DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
|
||||
pll_clocks, num, value), \
|
||||
.pll_den = \
|
||||
DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), \
|
||||
pll_clocks, den, value), \
|
||||
.mclk_pin_mask = \
|
||||
DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), \
|
||||
pinmuxes, 0, function), \
|
||||
.mclk_pin_offset = \
|
||||
DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), \
|
||||
pinmuxes, 0, pin), \
|
||||
.clk_sub_sys = (clock_control_subsys_t) \
|
||||
DT_INST_CLOCKS_CELL_BY_IDX(i2s_id, 0, name), \
|
||||
.pll_src = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, src, value), \
|
||||
.pll_lp = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, lp, value), \
|
||||
.pll_pd = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, pd, value), \
|
||||
.pll_num = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, num, value), \
|
||||
.pll_den = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, den, value), \
|
||||
.mclk_pin_mask = DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), pinmuxes, 0, function), \
|
||||
.mclk_pin_offset = DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), pinmuxes, 0, pin), \
|
||||
.clk_sub_sys = \
|
||||
(clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(i2s_id, 0, name), \
|
||||
.ccm_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(i2s_id)), \
|
||||
.irq_connect = i2s_irq_connect_##i2s_id, \
|
||||
.pinctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(i2s_id), \
|
||||
.tx_sync_mode = \
|
||||
DT_INST_PROP(i2s_id, nxp_tx_sync_mode), \
|
||||
.rx_sync_mode = \
|
||||
DT_INST_PROP(i2s_id, nxp_rx_sync_mode), \
|
||||
.tx_sync_mode = DT_INST_PROP(i2s_id, nxp_tx_sync_mode), \
|
||||
.rx_sync_mode = DT_INST_PROP(i2s_id, nxp_rx_sync_mode), \
|
||||
.tx_channel = DT_INST_PROP(i2s_id, nxp_tx_channel), \
|
||||
}; \
|
||||
\
|
||||
static struct i2s_dev_data i2s_##i2s_id##_data = { \
|
||||
.dev_dma = DEVICE_DT_GET( \
|
||||
DT_INST_DMAS_CTLR_BY_NAME(i2s_id, rx)), \
|
||||
.tx = { \
|
||||
.dma_channel = \
|
||||
DT_INST_PROP(i2s_id, nxp_tx_dma_channel), \
|
||||
.dma_cfg = { \
|
||||
.source_burst_length = \
|
||||
CONFIG_I2S_EDMA_BURST_SIZE, \
|
||||
.dest_burst_length = \
|
||||
CONFIG_I2S_EDMA_BURST_SIZE, \
|
||||
.dev_dma = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(i2s_id, rx)), \
|
||||
.tx = \
|
||||
{ \
|
||||
.dma_channel = DT_INST_PROP(i2s_id, nxp_tx_dma_channel), \
|
||||
.dma_cfg = \
|
||||
{ \
|
||||
.source_burst_length = CONFIG_I2S_EDMA_BURST_SIZE, \
|
||||
.dest_burst_length = CONFIG_I2S_EDMA_BURST_SIZE, \
|
||||
.dma_callback = i2s_dma_tx_callback, \
|
||||
.complete_callback_en = 1, \
|
||||
.error_callback_dis = 1, \
|
||||
.block_count = 1, \
|
||||
.head_block = \
|
||||
&i2s_##i2s_id##_data.tx.dma_block, \
|
||||
.head_block = &i2s_##i2s_id##_data.tx.dma_block, \
|
||||
.channel_direction = MEMORY_TO_PERIPHERAL, \
|
||||
.dma_slot = \
|
||||
DT_INST_DMAS_CELL_BY_NAME(i2s_id, \
|
||||
tx, source), \
|
||||
.dma_slot = DT_INST_DMAS_CELL_BY_NAME(i2s_id, tx, \
|
||||
source), \
|
||||
}, \
|
||||
}, \
|
||||
.rx = { \
|
||||
.dma_channel = \
|
||||
DT_INST_PROP(i2s_id, nxp_rx_dma_channel), \
|
||||
.dma_cfg = { \
|
||||
.source_burst_length = \
|
||||
CONFIG_I2S_EDMA_BURST_SIZE, \
|
||||
.dest_burst_length = \
|
||||
CONFIG_I2S_EDMA_BURST_SIZE, \
|
||||
.rx = \
|
||||
{ \
|
||||
.dma_channel = DT_INST_PROP(i2s_id, nxp_rx_dma_channel), \
|
||||
.dma_cfg = \
|
||||
{ \
|
||||
.source_burst_length = CONFIG_I2S_EDMA_BURST_SIZE, \
|
||||
.dest_burst_length = CONFIG_I2S_EDMA_BURST_SIZE, \
|
||||
.dma_callback = i2s_dma_rx_callback, \
|
||||
.complete_callback_en = 1, \
|
||||
.error_callback_dis = 1, \
|
||||
.block_count = 1, \
|
||||
.head_block = \
|
||||
&i2s_##i2s_id##_data.rx.dma_block, \
|
||||
.head_block = &i2s_##i2s_id##_data.rx.dma_block, \
|
||||
.channel_direction = PERIPHERAL_TO_MEMORY, \
|
||||
.dma_slot = \
|
||||
DT_INST_DMAS_CELL_BY_NAME(i2s_id, \
|
||||
rx, source), \
|
||||
.dma_slot = DT_INST_DMAS_CELL_BY_NAME(i2s_id, rx, \
|
||||
source), \
|
||||
}, \
|
||||
}, \
|
||||
}; \
|
||||
\
|
||||
DEVICE_DT_INST_DEFINE(i2s_id, &i2s_mcux_initialize, NULL, \
|
||||
&i2s_##i2s_id##_data, &i2s_##i2s_id##_config, \
|
||||
POST_KERNEL, \
|
||||
CONFIG_I2S_INIT_PRIORITY, &i2s_mcux_driver_api); \
|
||||
DEVICE_DT_INST_DEFINE(i2s_id, &i2s_mcux_initialize, NULL, &i2s_##i2s_id##_data, \
|
||||
&i2s_##i2s_id##_config, POST_KERNEL, CONFIG_I2S_INIT_PRIORITY, \
|
||||
&i2s_mcux_driver_api); \
|
||||
\
|
||||
static void i2s_irq_connect_##i2s_id(const struct device *dev) \
|
||||
{ \
|
||||
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(i2s_id, 0, irq), \
|
||||
DT_INST_IRQ_BY_IDX(i2s_id, 0, priority), \
|
||||
i2s_mcux_isr, \
|
||||
DT_INST_IRQ_BY_IDX(i2s_id, 0, priority), i2s_mcux_isr, \
|
||||
DEVICE_DT_INST_GET(i2s_id), 0); \
|
||||
irq_enable(DT_INST_IRQN(i2s_id)); \
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue