soc: arm: introduce NXP S32Z/E support

This patch introduces support for NXP S32 devices, specifically for
S32Z27 from S32Z/E family.

NXP S32Z27 processors are composed of two Real-Time Units (RTU)
containing each four ARM Cortex-R52 cores with flexible split/lock
configuration, and dedicated internal SRAM.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>

dts/arm/nxp/nxp_s32z27x_r52.dtsi

@@ -0,0 +1,96 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <1>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <3>;
+		};
+
+		cpu@4 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <4>;
+		};
+
+		cpu@5 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <5>;
+		};
+
+		cpu@6 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <6>;
+		};
+
+		cpu@7 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <7>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8_timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@47800000 {
+			compatible = "arm,gic";
+			reg = <0x47800000 0x10000>,
+				<0x47900000 0x80000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+		};
+
+		sram0: memory@31780000 {
+			compatible = "mmio-sram";
+			reg = <0x31780000 DT_SIZE_M(1)>;
+		};
+
+		sram1: memory@35780000 {
+			compatible = "mmio-sram";
+			reg = <0x35780000 DT_SIZE_M(1)>;
+		};
+	};
+};

dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/nxp/nxp_s32z27x_r52.dtsi>
+
+/ {
+
+	cpus {
+		/delete-node/ cpu@4;
+		/delete-node/ cpu@5;
+		/delete-node/ cpu@6;
+		/delete-node/ cpu@7;
+	};
+
+};

dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/nxp/nxp_s32z27x_r52.dtsi>
+
+/ {
+
+	cpus {
+		/delete-node/ cpu@0;
+		/delete-node/ cpu@1;
+		/delete-node/ cpu@2;
+		/delete-node/ cpu@3;
+	};
+
+};

modules/Kconfig

@@ -28,6 +28,7 @@ source "modules/Kconfig.mcux"
 source "modules/Kconfig.microchip"
 source "modules/Kconfig.nuvoton"
 source "modules/Kconfig.open-amp"
+source "modules/Kconfig.s32"
 source "modules/Kconfig.silabs"
 source "modules/Kconfig.simplelink"
 source "modules/Kconfig.sof"

modules/Kconfig.s32

@@ -0,0 +1,9 @@
+# NXP S32 MCUs family
+
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config HAS_S32_HAL
+	bool
+	select HAS_CMSIS_CORE
+	depends on SOC_FAMILY_S32

soc/arm/nxp_s32/CMakeLists.txt

@@ -0,0 +1,5 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})
+add_subdirectory(common)

soc/arm/nxp_s32/Kconfig

@@ -0,0 +1,18 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_S32
+	bool
+
+if SOC_FAMILY_S32
+
+config SOC_FAMILY
+	string
+	default "nxp_s32"
+
+source "soc/arm/nxp_s32/*/Kconfig.soc"
+
+config SOC_PART_NUMBER
+	default SOC_PART_NUMBER_S32ZE_R52 if SOC_SERIES_S32ZE_R52
+
+endif # SOC_FAMILY_S32

soc/arm/nxp_s32/Kconfig.defconfig

@@ -0,0 +1,4 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/arm/nxp_s32/*/Kconfig.defconfig.series"

soc/arm/nxp_s32/Kconfig.soc

@@ -0,0 +1,4 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/arm/nxp_s32/*/Kconfig.series"

soc/arm/nxp_s32/common/CMakeLists.txt

@@ -0,0 +1,4 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(osif.c)

soc/arm/nxp_s32/common/osif.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <OsIf.h>
+#include <OsIf_Cfg_TypesDef.h>
+
+#if defined(CONFIG_SOC_S32Z27_R52)
+#include <S32Z27_MSCM.h>
+#endif
+
+/* Required by OsIf timer initialization but not used with Zephyr, so no values configured */
+static const OsIf_ConfigType osif_config;
+const OsIf_ConfigType *const OsIf_apxPredefinedConfig[OSIF_MAX_COREIDX_SUPPORTED] = {
+	&osif_config
+};
+
+/*
+ * OsIf call to get the processor number of the core making the access.
+ */
+uint8_t Sys_GetCoreID(void)
+{
+	return ((uint8_t)(IP_MSCM->CPXNUM & MSCM_CPXNUM_CPN_MASK));
+}

soc/arm/nxp_s32/s32ze/CMakeLists.txt

@@ -0,0 +1,8 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources(
+  soc.c
+)
+
+zephyr_library_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c)

soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32z27

@@ -0,0 +1,9 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_S32Z27_R52
+
+config SOC
+	default "s32z27"
+
+endif # SOC_S32Z27_R52

soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series

@@ -0,0 +1,34 @@
+# NXP S32Z/E MCUs family default configuration
+
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_S32ZE_R52
+
+config SOC_SERIES
+	default "s32ze"
+
+config NUM_IRQS
+	# must be >= the highest interrupt number used
+	default 991
+
+config FPU
+	default y
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 2000000
+
+config MAIN_STACK_SIZE
+	default 1024
+
+if !XIP
+config FLASH_SIZE
+	default 0
+
+config FLASH_BASE_ADDRESS
+	default 0
+endif # !XIP
+
+source "soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32*"
+
+endif # SOC_SERIES_S32ZE_R52

soc/arm/nxp_s32/s32ze/Kconfig.series

@@ -0,0 +1,19 @@
+# NXP S32Z/E MCUs family
+
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_S32ZE_R52
+	bool "NXP S32Z/E series"
+	select ARM
+	select ARM_ARCH_TIMER
+	select CPU_CORTEX_R52
+	select CPU_HAS_DCLS
+	select CPU_HAS_ARM_MPU
+	select GIC_V3
+	select GIC_SINGLE_SECURITY_STATE
+	select VFP_DP_D16
+	select PLATFORM_SPECIFIC_INIT
+	select SOC_FAMILY_S32
+	help
+	  Enable support for NXP S32Z/E MCUs family on Cortex-R52 cores.

soc/arm/nxp_s32/s32ze/Kconfig.soc

@@ -0,0 +1,37 @@
+# NXP S32Z/E MCUs family
+
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "NXP S32Z/E MCUs family SoC selection"
+	depends on SOC_SERIES_S32ZE_R52
+
+config SOC_S32Z27_R52
+	bool "SOC_S32Z27_R52"
+	select HAS_S32_HAL
+
+endchoice
+
+if SOC_SERIES_S32ZE_R52
+
+config SOC_PART_NUMBER_S32Z27
+	bool
+
+config SOC_PART_NUMBER_S32ZE_R52
+	string
+	default "S32Z27" if SOC_PART_NUMBER_S32Z27
+	help
+	  This string holds the full part number of the SoC. It is a hidden option
+	  that you should not set directly. The part number selection choice defines
+	  the default value for this string.
+
+config INIT_CLOCK_AT_BOOT_TIME
+	bool "Initialize clocks at boot time"
+	default y
+	help
+	  Initialize clocks at boot time with the configuration generated through the
+	  driver's configurator, instead of using the default SoC clock configuration
+	  at reset.
+
+endif # SOC_SERIES_S32ZE_R52

soc/arm/nxp_s32/s32ze/linker.ld

@@ -0,0 +1,7 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/aarch32/cortex_a_r/scripts/linker.ld>

soc/arm/nxp_s32/s32ze/mpu_regions.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/linker/linker-defs.h>
+#include <zephyr/arch/arm/aarch32/mpu/arm_mpu.h>
+
+#define DEVICE_REGION_START 0x40000000UL
+#define DEVICE_REGION_END   0x76FFFFFFUL
+
+static const struct arm_mpu_region mpu_regions[] = {
+	MPU_REGION_ENTRY("vector",
+			 (uintptr_t)_vector_start,
+			 REGION_RAM_TEXT_ATTR((uintptr_t)_vector_end)),
+
+	MPU_REGION_ENTRY("SRAM_TEXT",
+			 (uintptr_t)__text_region_start,
+			 REGION_RAM_TEXT_ATTR((uintptr_t)__rodata_region_start)),
+
+	MPU_REGION_ENTRY("SRAM_RODATA",
+			 (uintptr_t)__rodata_region_start,
+			 REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end)),
+
+	MPU_REGION_ENTRY("SRAM_DATA",
+#ifdef CONFIG_USERSPACE
+			 (uintptr_t)_app_smem_start,
+#else
+			 (uintptr_t)__kernel_ram_start,
+#endif
+			 REGION_RAM_ATTR((uintptr_t)__kernel_ram_end)),
+
+	MPU_REGION_ENTRY("DEVICE",
+			 DEVICE_REGION_START,
+			 REGION_DEVICE_ATTR(DEVICE_REGION_END)),
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};

soc/arm/nxp_s32/s32ze/soc.c

@@ -0,0 +1,48 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+
+#include <OsIf.h>
+
+#ifdef CONFIG_INIT_CLOCK_AT_BOOT_TIME
+#include <Clock_Ip.h>
+#include <Clock_Ip_Cfg.h>
+#endif
+
+void z_arm_platform_init(void)
+{
+	/* enable peripheral port access at EL1 and EL0 */
+	__asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n");
+	__asm__ volatile("orr r0, #1\n");
+	__asm__ volatile("mcr p15, 0, r0, c15, c0, 0\n");
+	__DSB();
+	__ISB();
+}
+
+static int soc_init(const struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	/* Install default handler that simply resets the CPU if configured in the
+	 * kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	OsIf_Init(NULL);
+
+#ifdef CONFIG_INIT_CLOCK_AT_BOOT_TIME
+	/* Initialize clocks with tool generated code */
+	Clock_Ip_Init(Clock_Ip_aClockConfig);
+#endif
+
+	return 0;
+}
+
+SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/arm/nxp_s32/s32ze/soc.h

@@ -0,0 +1,13 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _NXP_S32_S32ZE_SOC_H_
+#define _NXP_S32_S32ZE_SOC_H_
+
+/* Do not let CMSIS to handle GIC */
+#define __GIC_PRESENT 0
+
+#endif /* _NXP_S32_S32ZE_SOC_H_ */

west.yml

@@ -88,7 +88,7 @@ manifest:
       groups:
         - hal
     - name: hal_nxp
-      revision: 708c95825b0d5279620935a1356299fff5dfbc6e
+      revision: 3e3648526824cc5b52ab59d5dd308473e291b760
       path: modules/hal/nxp
       groups:
         - hal