drivers: clock_contrl: Remove renesas,ra-clock-generation-circuit driver
Remove the renesas,ra-clock-generation-circuit driver, which is no longer needed after migrating to the FSP-based implementation. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit is contained in:
TOKITA Hiroshi
Fabio Baltieri
parent
f0219c35da
commit
43db55a79b
6 changed files with 0 additions and 431 deletions
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@ -33,7 +33,6 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_APB clock_cont
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SMARTBOND clock_control_smartbond.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NUMAKER_SCC clock_control_numaker_scc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_S32 clock_control_nxp_s32.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA clock_control_renesas_ra.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC clock_control_renesas_ra_cgc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ clock_control_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM clock_control_pwm.c)
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@ -84,8 +84,6 @@ source "drivers/clock_control/Kconfig.nxp_s32"
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source "drivers/clock_control/Kconfig.agilex5"
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source "drivers/clock_control/Kconfig.renesas_ra"
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source "drivers/clock_control/Kconfig.renesas_ra_cgc"
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source "drivers/clock_control/Kconfig.max32"
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@ -1,9 +0,0 @@
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# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_RENESAS_RA
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bool "Renesas RA series clock generation circuit driver"
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default y
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depends on DT_HAS_RENESAS_RA_CLOCK_GENERATION_CIRCUIT_ENABLED
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help
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Enable Renesas RA series clock generation circuit driver.
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@ -1,309 +0,0 @@
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/*
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* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#define DT_DRV_COMPAT renesas_ra_clock_generation_circuit
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/kernel.h>
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#include <soc.h>
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#include <zephyr/dt-bindings/clock/renesas-ra-cgc.h>
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#if DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, pll))
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#define SYSCLK_SRC pll
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#elif DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, mosc))
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#define SYSCLK_SRC mosc
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#elif DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, sosc))
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#define SYSCLK_SRC sosc
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#elif DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, hoco))
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#define SYSCLK_SRC hoco
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#elif DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, moco))
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#define SYSCLK_SRC moco
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#elif DT_SAME_NODE(DT_INST_PROP(0, clock_source), DT_PATH(clocks, loco))
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#define SYSCLK_SRC loco
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#else
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#error Unknown clock source
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#endif
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#define FREQ_iclk (clock_freqs[_CONCAT(SCRSCK_, SYSCLK_SRC)] / DT_INST_PROP(0, iclk_div))
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#define FREQ_pclka (clock_freqs[_CONCAT(SCRSCK_, SYSCLK_SRC)] / DT_INST_PROP(0, pclka_div))
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#define FREQ_pclkb (clock_freqs[_CONCAT(SCRSCK_, SYSCLK_SRC)] / DT_INST_PROP(0, pclkb_div))
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#define FREQ_pclkc (clock_freqs[_CONCAT(SCRSCK_, SYSCLK_SRC)] / DT_INST_PROP(0, pclkc_div))
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#define FREQ_pclkd (clock_freqs[_CONCAT(SCRSCK_, SYSCLK_SRC)] / DT_INST_PROP(0, pclkd_div))
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#define FREQ_fclk (clock_freqs[_CONCAT(SCRSCK_, SYSCLK_SRC)] / DT_INST_PROP(0, fclk_div))
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#define CLKSRC_FREQ(clk) DT_PROP(DT_PATH(clocks, clk), clock_frequency)
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#define IS_CLKSRC_ENABLED(clk) DT_NODE_HAS_STATUS_OKAY(DT_PATH(clocks, clk))
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#define SCKSCR_INIT_VALUE _CONCAT(CLKSRC_, SYSCLK_SRC)
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#define SCKDIV_ENABLED(clk) DT_INST_NODE_HAS_PROP(0, clk##_div)
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#define SCKDIV_VAL(clk) _CONCAT(SCKDIV_, DT_INST_PROP(0, clk##_div))
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#define SCKDIV_POS(clk) _CONCAT(SCKDIV_POS_, clk)
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#define SCKDIVCR_BITS(clk) \
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COND_CODE_1(SCKDIV_ENABLED(clk), ((SCKDIV_VAL(clk) & 0xFU) << SCKDIV_POS(clk)), (0U))
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#define SCKDIVCR_INIT_VALUE \
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(SCKDIVCR_BITS(iclk) | SCKDIVCR_BITS(pclka) | SCKDIVCR_BITS(pclkb) | \
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SCKDIVCR_BITS(pclkc) | SCKDIVCR_BITS(pclkd) | SCKDIVCR_BITS(bclk) | SCKDIVCR_BITS(fclk))
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#define HOCOWTCR_INIT_VALUE (6)
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/*
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* Required cycles for sub-clokc stabilizing.
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*/
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#define SUBCLK_STABILIZE_CYCLES 5
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extern int z_clock_hw_cycles_per_sec;
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enum {
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CLKSRC_hoco = 0,
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CLKSRC_moco,
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CLKSRC_loco,
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CLKSRC_mosc,
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CLKSRC_sosc,
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CLKSRC_pll,
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};
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enum {
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SCKDIV_1 = 0,
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SCKDIV_2,
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SCKDIV_4,
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SCKDIV_8,
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SCKDIV_16,
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SCKDIV_32,
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SCKDIV_64,
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SCKDIV_128,
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SCKDIV_3,
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SCKDIV_6,
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SCKDIV_12
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};
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enum {
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SCKDIV_POS_pclkd = 0x0U,
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SCKDIV_POS_pclkc = 0x4U,
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SCKDIV_POS_pclkb = 0x8U,
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SCKDIV_POS_pclka = 0xcU,
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SCKDIV_POS_bclk = 0x10U,
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SCKDIV_POS_pclke = 0x14U,
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SCKDIV_POS_iclk = 0x18U,
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SCKDIV_POS_fclk = 0x1cU
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};
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enum {
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OSCSF_HOCOSF_POS = 0,
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OSCSF_MOSCSF_POS = 3,
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OSCSF_PLLSF_POS = 5,
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};
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enum {
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OPCCR_OPCMTSF_POS = 4,
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};
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static const uint32_t PRCR_KEY = 0xA500U;
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static const uint32_t PRCR_CLOCKS = 0x1U;
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static const uint32_t PRCR_LOW_POWER = 0x2U;
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enum {
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#if DT_INST_REG_SIZE_BY_NAME(0, mstp) == 16
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MSTPCRA_OFFSET = -0x4,
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#else
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MSTPCRA_OFFSET = 0x0,
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#endif
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MSTPCRB_OFFSET = (MSTPCRA_OFFSET + 0x4),
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MSTPCRC_OFFSET = (MSTPCRB_OFFSET + 0x4),
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MSTPCRD_OFFSET = (MSTPCRC_OFFSET + 0x4),
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MSTPCRE_OFFSET = (MSTPCRD_OFFSET + 0x4),
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};
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enum {
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SCKDIVCR_OFFSET = 0x020,
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SCKSCR_OFFSET = 0x026,
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MEMWAIT_OFFSET = 0x031,
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MOSCCR_OFFSET = 0x032,
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HOCOCR_OFFSET = 0x036,
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OSCSF_OFFSET = 0x03C,
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CKOCR_OFFSET = 0x03E,
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OPCCR_OFFSET = 0x0A0,
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HOCOWTCR_OFFSET = 0x0A5,
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PRCR_OFFSET = 0x3FE,
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SOSCCR_OFFSET = 0x480,
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};
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enum {
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SCRSCK_hoco,
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SCRSCK_moco,
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SCRSCK_loco,
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SCRSCK_mosc,
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SCRSCK_sosc,
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SCRSCK_pll,
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};
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static const int clock_freqs[] = {
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COND_CODE_1(IS_CLKSRC_ENABLED(hoco), (CLKSRC_FREQ(hoco)), (0)),
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COND_CODE_1(IS_CLKSRC_ENABLED(moco), (CLKSRC_FREQ(moco)), (0)),
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COND_CODE_1(IS_CLKSRC_ENABLED(loco), (CLKSRC_FREQ(loco)), (0)),
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COND_CODE_1(IS_CLKSRC_ENABLED(mosc), (CLKSRC_FREQ(mosc)), (0)),
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COND_CODE_1(IS_CLKSRC_ENABLED(sosc), (CLKSRC_FREQ(sosc)), (0)),
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COND_CODE_1(IS_CLKSRC_ENABLED(pll),
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(DT_PROP(DT_PHANDLE_BY_IDX(DT_PATH(clocks, pll), clocks, 0), clock_frequency) *
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DT_PROP(DT_PATH(clocks, pll), clock_mult) /
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DT_PROP(DT_PATH(clocks, pll), clock_div)),
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(0)),
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};
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static uint32_t MSTP_read(size_t offset)
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{
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return sys_read32(DT_INST_REG_ADDR_BY_NAME(0, mstp) + offset);
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}
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static void MSTP_write(size_t offset, uint32_t value)
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{
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sys_write32(value, DT_INST_REG_ADDR_BY_NAME(0, mstp) + offset);
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}
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static uint8_t SYSTEM_read8(size_t offset)
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{
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return sys_read8(DT_INST_REG_ADDR_BY_NAME(0, system) + offset);
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}
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static void SYSTEM_write8(size_t offset, uint8_t value)
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{
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sys_write8(value, DT_INST_REG_ADDR_BY_NAME(0, system) + offset);
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}
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static void SYSTEM_write16(size_t offset, uint16_t value)
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{
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sys_write16(value, DT_INST_REG_ADDR_BY_NAME(0, system) + offset);
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}
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static void SYSTEM_write32(size_t offset, uint32_t value)
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{
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sys_write32(value, DT_INST_REG_ADDR_BY_NAME(0, system) + offset);
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}
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static int clock_control_ra_on(const struct device *dev, clock_control_subsys_t subsys)
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{
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uint32_t clkid = (uint32_t)subsys;
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int lock = irq_lock();
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MSTP_write(MSTPCRA_OFFSET + RA_CLOCK_GROUP(clkid),
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MSTP_read(MSTPCRB_OFFSET) & ~RA_CLOCK_BIT(clkid));
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irq_unlock(lock);
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return 0;
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}
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static int clock_control_ra_off(const struct device *dev, clock_control_subsys_t subsys)
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{
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uint32_t clkid = (uint32_t)subsys;
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int lock = irq_lock();
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MSTP_write(MSTPCRA_OFFSET + RA_CLOCK_GROUP(clkid),
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MSTP_read(MSTPCRB_OFFSET) | RA_CLOCK_BIT(clkid));
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irq_unlock(lock);
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return 0;
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}
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static int clock_control_ra_get_rate(const struct device *dev, clock_control_subsys_t subsys,
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uint32_t *rate)
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{
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uint32_t clkid = (uint32_t)subsys;
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switch (clkid & 0xFFFFFF00) {
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case RA_CLOCK_SCI(0):
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*rate = FREQ_pclka;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct clock_control_driver_api ra_clock_control_driver_api = {
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.on = clock_control_ra_on,
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.off = clock_control_ra_off,
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.get_rate = clock_control_ra_get_rate,
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};
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static void crude_busy_loop_impl(uint32_t cycles)
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{
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__asm__ volatile(".align 8\n"
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"busy_loop:\n"
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" sub r0, r0, #1\n"
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" cmp r0, #0\n"
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" bne.n busy_loop\n");
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}
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static inline void crude_busy_loop(uint32_t wait_us)
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{
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static const uint64_t cycles_per_loop = 4;
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crude_busy_loop_impl(sys_clock_hw_cycles_per_sec() * wait_us / USEC_PER_SEC /
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cycles_per_loop);
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}
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static int clock_control_ra_init(const struct device *dev)
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{
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uint8_t sysclk = SYSTEM_read8(SCKSCR_OFFSET);
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z_clock_hw_cycles_per_sec = clock_freqs[sysclk];
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SYSTEM_write16(PRCR_OFFSET, PRCR_KEY | PRCR_CLOCKS | PRCR_LOW_POWER);
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if (clock_freqs[SCRSCK_hoco] == 64000000) {
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SYSTEM_write8(HOCOWTCR_OFFSET, HOCOWTCR_INIT_VALUE);
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}
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SYSTEM_write8(SOSCCR_OFFSET, !IS_CLKSRC_ENABLED(sosc));
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SYSTEM_write8(MOSCCR_OFFSET, !IS_CLKSRC_ENABLED(mosc));
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SYSTEM_write8(HOCOCR_OFFSET, !IS_CLKSRC_ENABLED(hoco));
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if (IS_CLKSRC_ENABLED(sosc)) {
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crude_busy_loop(z_clock_hw_cycles_per_sec / clock_freqs[CLKSRC_sosc] *
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SUBCLK_STABILIZE_CYCLES);
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}
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if (IS_CLKSRC_ENABLED(mosc)) {
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while ((SYSTEM_read8(OSCSF_OFFSET) & BIT(OSCSF_MOSCSF_POS)) !=
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BIT(OSCSF_MOSCSF_POS)) {
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;
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}
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}
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if (IS_CLKSRC_ENABLED(hoco)) {
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while ((SYSTEM_read8(OSCSF_OFFSET) & BIT(OSCSF_HOCOSF_POS)) !=
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BIT(OSCSF_HOCOSF_POS)) {
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;
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}
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}
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SYSTEM_write8(OPCCR_OFFSET, 0);
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while ((SYSTEM_read8(OPCCR_OFFSET) & BIT(OPCCR_OPCMTSF_POS)) != 0) {
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;
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}
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SYSTEM_write8(MEMWAIT_OFFSET, 1);
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SYSTEM_write32(SCKDIVCR_OFFSET, SCKDIVCR_INIT_VALUE);
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SYSTEM_write8(SCKSCR_OFFSET, SCKSCR_INIT_VALUE);
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/* re-read system clock setting and apply to hw_cycles */
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sysclk = SYSTEM_read8(SCKSCR_OFFSET);
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z_clock_hw_cycles_per_sec = clock_freqs[sysclk];
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SYSTEM_write16(PRCR_OFFSET, PRCR_KEY);
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0, clock_control_ra_init, NULL, NULL, NULL, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &ra_clock_control_driver_api);
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@ -1,46 +0,0 @@
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# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RA series Clock Generation Circuit
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compatible: "renesas,ra-clock-generation-circuit"
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include: [clock-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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iclk-div:
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type: int
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description: Division factor for ICLK
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fclk-div:
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type: int
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description: Division factor for FCLK
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pclka-div:
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type: int
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description: Division factor for PCLKA
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pclkb-div:
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type: int
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description: Division factor for PCLKB
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pclkc-div:
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type: int
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description: Division factor for PCLKC
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pclkd-div:
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type: int
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description: Division factor for PCLKD
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clock-source:
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type: phandle
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description: System clock source
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"#clock-cells":
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const: 1
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clock-cells:
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- id
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@ -1,64 +0,0 @@
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/*
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* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DT_BINDINGS_CLOCK_RENESAS_RA_CGC_H_
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#define ZEPHYR_DT_BINDINGS_CLOCK_RENESAS_RA_CGC_H_
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#define RA_CLOCK(grp, func, ch) ((grp << 28) | (func << 20) | ch)
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#define RA_CLOCK_GROUP(mod) (((mod >> 28) & 0xF) * 4)
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#define RA_CLOCK_BIT(mod) BIT(((mod >> 20) & 0xFF) - ((mod >> 0) & 0xF))
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#define RA_CLOCK_DMAC(channel) RA_CLOCK(0, 22, channel)
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#define RA_CLOCK_DTC(channel) RA_CLOCK(0, 22, channel)
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#define RA_CLOCK_CAN(channel) RA_CLOCK(1, 2, channel)
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#define RA_CLOCK_CEC(channel) RA_CLOCK(1, 3U, channel)
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#define RA_CLOCK_I3C(channel) RA_CLOCK(1, 4U, channel)
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#define RA_CLOCK_IRDA(channel) RA_CLOCK(1, 5U, channel)
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#define RA_CLOCK_QSPI(channel) RA_CLOCK(1, 6U, channel)
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#define RA_CLOCK_IIC(channel) RA_CLOCK(1, 9U, channel)
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#define RA_CLOCK_USBFS(channel) RA_CLOCK(1, 11U, channel)
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#define RA_CLOCK_USBHS(channel) RA_CLOCK(1, 12U, channel)
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#define RA_CLOCK_EPTPC(channel) RA_CLOCK(1, 13U, channel)
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#define RA_CLOCK_ETHER(channel) RA_CLOCK(1, 15U, channel)
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#define RA_CLOCK_OSPI(channel) RA_CLOCK(1, 16U, channel)
|
||||
#define RA_CLOCK_SPI(channel) RA_CLOCK(1, 19U, channel)
|
||||
#define RA_CLOCK_SCI(channel) RA_CLOCK(1, 31U, channel)
|
||||
#define RA_CLOCK_CAC(channel) RA_CLOCK(2, 0U, channel)
|
||||
#define RA_CLOCK_CRC(channel) RA_CLOCK(2, 1U, channel)
|
||||
#define RA_CLOCK_PDC(channel) RA_CLOCK(2, 2U, channel)
|
||||
#define RA_CLOCK_CTSU(channel) RA_CLOCK(2, 3U, channel)
|
||||
#define RA_CLOCK_SLCDC(channel) RA_CLOCK(2, 4U, channel)
|
||||
#define RA_CLOCK_GLCDC(channel) RA_CLOCK(2, 4U, channel)
|
||||
#define RA_CLOCK_JPEG(channel) RA_CLOCK(2, 5U, channel)
|
||||
#define RA_CLOCK_DRW(channel) RA_CLOCK(2, 6U, channel)
|
||||
#define RA_CLOCK_SSI(channel) RA_CLOCK(2, 8U, channel)
|
||||
#define RA_CLOCK_SRC(channel) RA_CLOCK(2, 9U, channel)
|
||||
#define RA_CLOCK_SDHIMMC(channel) RA_CLOCK(2, 12U, channel)
|
||||
#define RA_CLOCK_DOC(channel) RA_CLOCK(2, 13U, channel)
|
||||
#define RA_CLOCK_ELC(channel) RA_CLOCK(2, 14U, channel)
|
||||
#define RA_CLOCK_CEU(channel) RA_CLOCK(2, 16U, channel)
|
||||
#define RA_CLOCK_TFU(channel) RA_CLOCK(2, 20U, channel)
|
||||
#define RA_CLOCK_IIRFA(channel) RA_CLOCK(2, 21U, channel)
|
||||
#define RA_CLOCK_CANFD(channel) RA_CLOCK(2, 27U, channel)
|
||||
#define RA_CLOCK_TRNG(channel) RA_CLOCK(2, 28U, channel)
|
||||
#define RA_CLOCK_SCE(channel) RA_CLOCK(2, 31U, channel)
|
||||
#define RA_CLOCK_AES(channel) RA_CLOCK(2, 31U, channel)
|
||||
#define RA_CLOCK_POEG(channel) RA_CLOCK(3, 14U, channel)
|
||||
#define RA_CLOCK_ADC(channel) RA_CLOCK(3, 16U, channel)
|
||||
#define RA_CLOCK_SDADC(channel) RA_CLOCK(3, 17U, channel)
|
||||
#define RA_CLOCK_DAC8(channel) RA_CLOCK(3, 19U, channel)
|
||||
#define RA_CLOCK_DAC(channel) RA_CLOCK(3, 20U, channel)
|
||||
#define RA_CLOCK_TSN(channel) RA_CLOCK(3, 22U, channel)
|
||||
#define RA_CLOCK_ACMPHS(channel) RA_CLOCK(3, 28U, channel)
|
||||
#define RA_CLOCK_ACMPLP(channel) RA_CLOCK(3, 29U, channel)
|
||||
#define RA_CLOCK_OPAMP(channel) RA_CLOCK(3, 31U, channel)
|
||||
#define RA_CLOCK_AGT(channel) RA_CLOCK(4, 3U, channel)
|
||||
#define RA_CLOCK_KEY(channel) RA_CLOCK(4, 4U, channel)
|
||||
#define RA_CLOCK_ULPT(channel) RA_CLOCK(4, 9U, channel)
|
||||
#define RA_CLOCK_GPT(channel) RA_CLOCK(5, 31U, channel)
|
||||
|
||||
#endif /* ZEPHYR_DT_BINDINGS_CLOCK_RENESAS_RA_CGC_H_ */
|
||||
Loading…
Reference in a new issue