adafruit-mirror/zephyr
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions 9

dts: nrf5340: add missing GPIOTE1 in secure DTSI

Browse source 
GPIOTE1 on the nRF5340 SoC is always accessible as a non-secure
peripheral. However, it is only defined in the non-secure DTSI file.
This is therefore a missing node in the secure DTSI file, since
non-secure addresses are accessible by secure software.

Move the node definition to a common include file and pull it into the
app core DTSI as well. To keep things clean, adjust the node labels so
that:

- 'gpiote0' and 'gpiote1' are defined in the secure DTSI
- 'gpiote0' is not defined in the non-secure DTSI
- 'gpiote' is defined in both secure and non-secure DTSIs
- 'gpiote' refers to the same node as 'gpiote0' in the secure DTSI
- 'gpiote' refers to the same node as 'gpiote1' in the non-secure DTSI

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This commit is contained in:
Martí Bolívar 2021-05-21 14:37:22 -07:00 committed by Ioannis Glaropoulos
parent f4473f6a37
commit 4b54d363e8
3 changed files with 43 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
dts/arm/nordic/nrf5340_cpuapp.dtsi
View file

@ -63,7 +63,12 @@
};
};
gpiote: gpiote@5000d000 {
/*
* GPIOTE0 is always accessible as a secure peripheral,
* so we give it the 'gpiote' label for use when building
* code for this target.
*/
gpiote: gpiote0: gpiote@5000d000 {
compatible = "nordic,nrf-gpiote";
reg = <0x5000d000 0x1000>;
interrupts = <13 5>;
@ -95,3 +100,10 @@
&nvic {
arm,num-irq-priority-bits = <3>;
};
/*
* Include the non-secure peripherals file here since
* it expects to be at the root level. This provides
* a node for GPIOTE1.
*/
#include "nrf5340_cpuapp_peripherals_ns.dtsi"

21
dts/arm/nordic/nrf5340_cpuapp_peripherals_ns.dtsi Normal file
View file

@ -0,0 +1,21 @@
/*
* Copyright (c) 2019 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* GPIOTE1 is always accessible as a non-secure peripheral.
*/
/ {
soc {
gpiote1: gpiote@4002f000 {
compatible = "nordic,nrf-gpiote";
reg = <0x4002f000 0x1000>;
interrupts = <47 5>;
status = "disabled";
label = "GPIOTE_1";
};
};
};

17
dts/arm/nordic/nrf5340_cpuappns.dtsi
View file

@ -48,17 +48,18 @@
#include "nrf5340_cpuapp_peripherals.dtsi"
};
/* Additional Non-Secure peripherals */
gpiote: gpiote@4002f000 {
compatible = "nordic,nrf-gpiote";
reg = <0x4002f000 0x1000>;
interrupts = <47 5>;
status = "disabled";
label = "GPIOTE_1";
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};
/*
* Include the non-secure peripherals file here since
* it expects to be at the root level, adding a 'gpiote' label
* for the GPIOTE1 peripheral defined in that file which is
* always accessible as a non-secure peripheral.
*/
#include "nrf5340_cpuapp_peripherals_ns.dtsi"
gpiote: &gpiote1 {};