drivers: serial: add RZT2M uart driver
This adds a UART driver for the Renesas RZ/T2M Serial Communication Interface. The driver implements: * Polling API, * Interrupt-driven API. Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This commit is contained in:
Wojciech Sipak
Carles Cufí
parent
b1c83c0335
commit
4e35d0e354
9 changed files with 639 additions and 0 deletions
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@ -13,5 +13,15 @@
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chosen {
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zephyr,sram = &cpu0_atcm;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart3 {
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status = "okay";
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};
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@ -3,3 +3,8 @@
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CONFIG_SOC_RENESAS_RZT2M=y
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CONFIG_BOARD_RZT2M_STARTER_KIT=y
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CONFIG_SERIAL=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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@ -67,6 +67,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_SEDI uart_sedi.c)
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zephyr_library_sources_ifdef(CONFIG_UART_BCM2711_MU uart_bcm2711.c)
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zephyr_library_sources_ifdef(CONFIG_UART_INTEL_LW uart_intel_lw.c)
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zephyr_library_sources_ifdef(CONFIG_UART_RA uart_ra.c)
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zephyr_library_sources_ifdef(CONFIG_UART_RZT2M uart_rzt2m.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c)
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@ -255,4 +255,6 @@ source "drivers/serial/Kconfig.intel_lw"
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source "drivers/serial/Kconfig.ra"
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source "drivers/serial/Kconfig.rzt2m"
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endif # SERIAL
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11
drivers/serial/Kconfig.rzt2m
Normal file
11
drivers/serial/Kconfig.rzt2m
Normal file
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@ -0,0 +1,11 @@
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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config UART_RZT2M
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bool "Renesas RZ/T2M UART Driver"
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default y
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depends on DT_HAS_RENESAS_RZT2M_UART_ENABLED
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select SERIAL_HAS_DRIVER
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select SERIAL_SUPPORT_INTERRUPT
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help
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Enable Renesas RZ/T2M UART Driver.
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435
drivers/serial/uart_rzt2m.c
Normal file
435
drivers/serial/uart_rzt2m.c
Normal file
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@ -0,0 +1,435 @@
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/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "uart_rzt2m.h"
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#include "zephyr/spinlock.h"
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#include "zephyr/sys/printk.h"
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#include <zephyr/drivers/uart.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/irq.h>
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#include <stdint.h>
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#include <zephyr/logging/log.h>
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#include <soc.h>
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#define DT_DRV_COMPAT renesas_rzt2m_uart
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LOG_MODULE_REGISTER(uart_renesas_rzt2m, CONFIG_UART_LOG_LEVEL);
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struct rzt2m_device_config {
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mm_reg_t base;
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uart_irq_config_func_t irq_config_func;
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};
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struct rzt2m_device_data {
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struct uart_config uart_cfg;
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struct k_spinlock lock;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t callback;
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void *callback_data;
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#endif
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};
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static int rzt2m_poll_in(const struct device *dev, unsigned char *c)
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{
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if (!dev || !dev->config || !dev->data) {
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return -ENODEV;
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}
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const struct rzt2m_device_config *config = dev->config;
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struct rzt2m_device_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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if (FRSR_R(*FRSR(config->base)) == 0) {
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k_spin_unlock(&data->lock, key);
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return -1;
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}
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*c = *RDR(config->base) & RDR_MASK_RDAT;
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*CFCLR(config->base) |= CFCLR_MASK_RDRFC;
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if (FRSR_R(*FRSR(config->base)) == 0) {
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*FFCLR(config->base) |= FFCLR_MASK_DRC;
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}
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static void rzt2m_poll_out(const struct device *dev, unsigned char c)
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{
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if (!dev || !dev->config || !dev->data) {
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return;
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}
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const struct rzt2m_device_config *config = dev->config;
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struct rzt2m_device_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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int fifo_count = FTSR_T(*FTSR(config->base));
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while (fifo_count == MAX_FIFO_DEPTH) {
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fifo_count = FTSR_T(*FTSR(config->base));
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}
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*TDR(config->base) = c;
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/* Clear `Transmit data empty flag`. */
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*CFCLR(config->base) |= CFCLR_MASK_TDREC;
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k_spin_unlock(&data->lock, key);
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}
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static int rzt2m_err_check(const struct device *dev)
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{
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const struct rzt2m_device_config *config = dev->config;
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uint32_t status = *CSR(config->base);
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uint32_t retval = 0;
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if (status & CSR_MASK_ORER) {
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retval |= UART_ERROR_OVERRUN;
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}
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if (status & CSR_MASK_FER) {
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retval |= UART_ERROR_FRAMING;
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}
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if (status & CSR_MASK_PER) {
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retval |= UART_ERROR_PARITY;
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}
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return retval;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_rzt2m_irq_tx_ready(const struct device *dev);
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static int rzt2m_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
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{
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struct rzt2m_device_data *data = dev->data;
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const struct rzt2m_device_config *config = dev->config;
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int num_tx = 0;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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while ((size - num_tx > 0) && uart_rzt2m_irq_tx_ready(dev)) {
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*TDR(config->base) = (uint8_t)tx_data[num_tx++];
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}
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k_spin_unlock(&data->lock, key);
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return num_tx;
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}
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static int rzt2m_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
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{
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struct rzt2m_device_data *data = dev->data;
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const struct rzt2m_device_config *config = dev->config;
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int num_rx = 0;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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while (num_rx < size && (FRSR_R(*FRSR(config->base)))) {
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rx_data[num_rx++] = *RDR(config->base);
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}
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*CFCLR(config->base) = CFCLR_MASK_RDRFC;
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*FFCLR(config->base) = FFCLR_MASK_DRC;
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k_spin_unlock(&data->lock, key);
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return num_rx;
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}
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static void uart_rzt2m_irq_rx_enable(const struct device *dev)
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{
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const struct rzt2m_device_config *config = dev->config;
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*CCR0(config->base) |= CCR0_MASK_RIE | CCR0_MASK_RE;
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}
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static void uart_rzt2m_irq_rx_disable(const struct device *dev)
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{
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const struct rzt2m_device_config *config = dev->config;
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*CCR0(config->base) &= ~CCR0_MASK_RIE;
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}
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static void uart_rzt2m_irq_tx_enable(const struct device *dev)
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{
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const struct rzt2m_device_config *config = dev->config;
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/* These bits must be set simultaneously. */
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*CCR0(config->base) |= CCR0_MASK_TE | CCR0_MASK_TIE | CCR0_MASK_TEIE;
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}
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static void uart_rzt2m_irq_tx_disable(const struct device *dev)
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{
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const struct rzt2m_device_config *config = dev->config;
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*CCR0(config->base) &= ~(CCR0_MASK_TIE | CCR0_MASK_TEIE);
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}
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static int uart_rzt2m_irq_tx_ready(const struct device *dev)
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{
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const struct rzt2m_device_config *config = dev->config;
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if (FTSR_T(*FTSR(config->base)) == MAX_FIFO_DEPTH ||
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((*CCR0(config->base) & CCR0_MASK_TIE) == 0)) {
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return 0;
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}
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return 1;
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}
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static int uart_rzt2m_irq_rx_ready(const struct device *dev)
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{
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const struct rzt2m_device_config *config = dev->config;
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if (FRSR_R(*FRSR(config->base))) {
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return 1;
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}
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return 0;
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}
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static int uart_rzt2m_irq_is_pending(const struct device *dev)
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{
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const struct rzt2m_device_config *config = dev->config;
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if ((*CSR(config->base) & (CSR_MASK_RDRF)) || (*FRSR(config->base) & FRSR_MASK_DR)) {
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return 1;
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}
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return 0;
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}
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static void uart_rzt2m_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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struct rzt2m_device_data *data = dev->data;
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data->callback = cb;
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data->callback_data = cb_data;
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}
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static int uart_rzt2m_irq_update(const struct device *dev)
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{
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const struct rzt2m_device_config *config = dev->config;
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*CFCLR(config->base) = CFCLR_MASK_RDRFC;
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*FFCLR(config->base) = FFCLR_MASK_DRC;
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return 1;
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static const struct uart_driver_api rzt2m_uart_api = {
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.poll_in = rzt2m_poll_in,
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.poll_out = rzt2m_poll_out,
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.err_check = rzt2m_err_check,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = rzt2m_fifo_fill,
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.fifo_read = rzt2m_fifo_read,
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.irq_rx_enable = uart_rzt2m_irq_rx_enable,
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.irq_rx_disable = uart_rzt2m_irq_rx_disable,
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.irq_tx_enable = uart_rzt2m_irq_tx_enable,
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.irq_tx_disable = uart_rzt2m_irq_tx_disable,
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.irq_tx_ready = uart_rzt2m_irq_tx_ready,
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.irq_rx_ready = uart_rzt2m_irq_rx_ready,
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.irq_is_pending = uart_rzt2m_irq_is_pending,
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.irq_callback_set = uart_rzt2m_irq_callback_set,
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.irq_update = uart_rzt2m_irq_update,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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static int rzt2m_module_start(const struct device *dev)
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{
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if (!dev || !dev->config || !dev->data) {
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return -ENODEV;
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}
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const struct rzt2m_device_config *config = dev->config;
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struct rzt2m_device_data *data = dev->data;
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int interface_id = BASE_TO_IFACE_ID(config->base);
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unsigned int irqkey = irq_lock();
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volatile uint32_t dummy;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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if (interface_id < 5) {
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/* Dummy-read at least one time as stated in 8.3.1 of the User's Manual: Hardware */
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*MSTPCRA &= ~(MSTPCRA_MASK_SCIx(interface_id));
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dummy = *MSTPCRA;
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} else {
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LOG_ERR("SCI modules in the secure domain on RZT2M are not supported.");
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return -ENOTSUP;
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}
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/* Dummy-read at least five times as stated in 8.3.1 of the User's Manual: Hardware */
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dummy = *RDR(config->base);
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dummy = *RDR(config->base);
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dummy = *RDR(config->base);
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dummy = *RDR(config->base);
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dummy = *RDR(config->base);
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k_spin_unlock(&data->lock, key);
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irq_unlock(irqkey);
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return 0;
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}
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static int rzt2m_uart_init(const struct device *dev)
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{
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const struct rzt2m_device_config *config = dev->config;
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struct rzt2m_device_data *data = dev->data;
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uint32_t baud_setting = 0;
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uint32_t baud_settings[] = {CCR2_BAUD_SETTING_9600, CCR2_BAUD_SETTING_115200};
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rzt2m_unlock_prcrs(PRCRS_GPIO);
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rzt2m_unlock_prcrn(PRCRN_PRC1 | PRCRN_PRC2);
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/* The module needs to be started
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* to allow any operation on the registers of Serial Communications Interface.
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*/
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int ret = rzt2m_module_start(dev);
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if (ret) {
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return ret;
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}
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/* Disable transmitter, receiver, interrupts. */
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*CCR0(config->base) = CCR0_DEFAULT_VALUE;
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while (*CCR0(config->base) & (CCR0_MASK_RE | CCR0_MASK_TE)) {
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}
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*CCR1(config->base) = CCR1_DEFAULT_VALUE;
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*CCR2(config->base) = CCR2_DEFAULT_VALUE;
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*CCR3(config->base) = CCR3_DEFAULT_VALUE;
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*CCR4(config->base) = CCR4_DEFAULT_VALUE;
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*CFCLR(config->base) = CFCLR_ALL_FLAG_CLEAR;
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*FFCLR(config->base) = FFCLR_MASK_DRC;
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/* Use FIFO mode. */
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*CCR3(config->base) |= (CCR3_MASK_FM);
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switch (data->uart_cfg.stop_bits) {
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case UART_CFG_STOP_BITS_1:
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/* Default value, already set. */
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break;
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case UART_CFG_STOP_BITS_2:
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*CCR3(config->base) |= CCR3_MASK_STP;
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break;
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default:
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LOG_ERR("Selected bit stop length is not supported: %u.", data->uart_cfg.stop_bits);
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return -ENOTSUP;
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}
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switch (data->uart_cfg.data_bits) {
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case UART_CFG_DATA_BITS_7:
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*CCR3(config->base) |= CCR3_CHR_7BIT;
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break;
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case UART_CFG_DATA_BITS_8:
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*CCR3(config->base) |= CCR3_CHR_8BIT;
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break;
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default:
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LOG_ERR("Selected number of data bits is not supported: %u.",
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data->uart_cfg.data_bits);
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return -ENOTSUP;
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}
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if (data->uart_cfg.baudrate > ARRAY_SIZE(baud_settings)) {
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LOG_ERR("Selected baudrate variant is not supported: %u.", data->uart_cfg.baudrate);
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return -ENOTSUP;
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}
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baud_setting = baud_settings[data->uart_cfg.baudrate];
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*CCR2(config->base) &= ~(CCR2_MASK_BAUD_SETTING);
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*CCR2(config->base) |= (baud_setting & CCR2_MASK_BAUD_SETTING);
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*CCR1(config->base) |= (CCR1_MASK_NFEN | CCR1_MASK_SPB2DT | CCR1_MASK_SPB2IO);
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switch (data->uart_cfg.parity) {
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case UART_CFG_PARITY_NONE:
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/* Default value, already set. */
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break;
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case UART_CFG_PARITY_EVEN:
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*CCR1(config->base) |= CCR1_MASK_PE;
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break;
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case UART_CFG_PARITY_ODD:
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*CCR1(config->base) |= (CCR1_MASK_PE | CCR1_MASK_PM);
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break;
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default:
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LOG_ERR("Unsupported parity: %u", data->uart_cfg.parity);
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}
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/* Specify trigger thresholds and clear FIFOs. */
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*FCR(config->base) = FCR_MASK_TFRST | FCR_MASK_RFRST | FCR_TTRG_15 | FCR_RTRG_15;
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/* Enable the clock. */
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*CCR3(config->base) &= ~CCR3_MASK_CKE;
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*CCR3(config->base) |= CCR3_CKE_ENABLE;
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/* Clear status flags. */
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*CFCLR(config->base) = CFCLR_ALL_FLAG_CLEAR;
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*FFCLR(config->base) = FFCLR_MASK_DRC;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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config->irq_config_func(dev);
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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/* Start trasmitter and receiver. */
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*CCR0(config->base) |= (CCR0_MASK_TE | CCR0_MASK_RE);
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while (!(*CCR0(config->base) & CCR0_MASK_RE)) {
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}
|
||||
while (!(*CCR0(config->base) & CCR0_MASK_TE)) {
|
||||
}
|
||||
|
||||
rzt2m_lock_prcrs(PRCRS_GPIO);
|
||||
rzt2m_lock_prcrn(PRCRN_PRC1 | PRCRN_PRC2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void uart_rzt2m_isr(const struct device *dev)
|
||||
{
|
||||
const struct rzt2m_device_config *config = dev->config;
|
||||
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
||||
struct rzt2m_device_data *data = dev->data;
|
||||
|
||||
if (data->callback) {
|
||||
data->callback(dev, data->callback_data);
|
||||
}
|
||||
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
||||
|
||||
*CFCLR(config->base) = CFCLR_MASK_RDRFC;
|
||||
*FFCLR(config->base) = FFCLR_MASK_DRC;
|
||||
}
|
||||
|
||||
#define UART_RZT2M_IRQ_CONNECT(n, irq_name) \
|
||||
do { \
|
||||
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, irq_name, irq), \
|
||||
DT_INST_IRQ_BY_NAME(n, irq_name, priority), uart_rzt2m_isr, \
|
||||
DEVICE_DT_INST_GET(n), DT_INST_IRQ_BY_NAME(n, irq_name, flags)); \
|
||||
irq_enable(DT_INST_IRQ_BY_NAME(n, irq_name, irq)); \
|
||||
} while (false)
|
||||
|
||||
#define UART_RZT2M_CONFIG_FUNC(n) \
|
||||
static void uart##n##_rzt2m_irq_config(const struct device *port) \
|
||||
{ \
|
||||
UART_RZT2M_IRQ_CONNECT(n, rx_err); \
|
||||
UART_RZT2M_IRQ_CONNECT(n, rx); \
|
||||
UART_RZT2M_IRQ_CONNECT(n, tx); \
|
||||
UART_RZT2M_IRQ_CONNECT(n, tx_end); \
|
||||
}
|
||||
|
||||
#define UART_RZT2M_INIT(n) \
|
||||
static struct rzt2m_device_data rzt2m_uart_##n##data = { \
|
||||
.uart_cfg = \
|
||||
{ \
|
||||
.baudrate = DT_INST_ENUM_IDX(n, current_speed), \
|
||||
.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE), \
|
||||
.stop_bits = \
|
||||
DT_INST_ENUM_IDX_OR(n, stop_bits, UART_CFG_STOP_BITS_1), \
|
||||
.data_bits = \
|
||||
DT_INST_ENUM_IDX_OR(n, data_bits, UART_CFG_DATA_BITS_8), \
|
||||
}, \
|
||||
}; \
|
||||
UART_RZT2M_CONFIG_FUNC(n); \
|
||||
static const struct rzt2m_device_config rzt2m_uart_##n##_config = { \
|
||||
.base = DT_INST_REG_ADDR(n), .irq_config_func = uart##n##_rzt2m_irq_config}; \
|
||||
DEVICE_DT_INST_DEFINE(n, &rzt2m_uart_init, NULL, &rzt2m_uart_##n##data, \
|
||||
&rzt2m_uart_##n##_config, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
|
||||
&rzt2m_uart_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(UART_RZT2M_INIT)
|
||||
124
drivers/serial/uart_rzt2m.h
Normal file
124
drivers/serial/uart_rzt2m.h
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Antmicro <www.antmicro.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_DRIVERS_SERIAL_UART_RZT2M_H_
|
||||
#define ZEPHYR_DRIVERS_SERIAL_UART_RZT2M_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define MAX_FIFO_DEPTH 16
|
||||
|
||||
#define RDR(base) ((volatile uint32_t *)(base))
|
||||
#define TDR(base) ((volatile uint32_t *)(base + 0x04))
|
||||
#define CCR0(base) ((volatile uint32_t *)(base + 0x08))
|
||||
#define CCR1(base) ((volatile uint32_t *)(base + 0x0c))
|
||||
#define CCR2(base) ((volatile uint32_t *)(base + 0x10))
|
||||
#define CCR3(base) ((volatile uint32_t *)(base + 0x14))
|
||||
#define CCR4(base) ((volatile uint32_t *)(base + 0x18))
|
||||
#define FCR(base) ((volatile uint32_t *)(base + 0x24))
|
||||
#define CSR(base) ((volatile uint32_t *)(base + 0x48))
|
||||
#define FRSR(base) ((volatile uint32_t *)(base + 0x50))
|
||||
#define FTSR(base) ((volatile uint32_t *)(base + 0x54))
|
||||
#define CFCLR(base) ((volatile uint32_t *)(base + 0x68))
|
||||
#define FFCLR(base) ((volatile uint32_t *)(base + 0x70))
|
||||
|
||||
#define CCR0_DEFAULT_VALUE 0x0
|
||||
#define CCR1_DEFAULT_VALUE 0x00000010
|
||||
#define CCR2_DEFAULT_VALUE 0xff00ff04
|
||||
#define CCR3_DEFAULT_VALUE 0x00001203
|
||||
#define CCR4_DEFAULT_VALUE 0x0
|
||||
|
||||
#define RDR_MASK_RDAT GENMASK(8, 0)
|
||||
|
||||
#define CCR0_MASK_RE BIT(0)
|
||||
#define CCR0_MASK_TE BIT(4)
|
||||
#define CCR0_MASK_DCME BIT(9)
|
||||
#define CCR0_MASK_IDSEL BIT(10)
|
||||
#define CCR0_MASK_RIE BIT(16)
|
||||
#define CCR0_MASK_TIE BIT(20)
|
||||
#define CCR0_MASK_TEIE BIT(21)
|
||||
#define CCR0_MASK_SSE BIT(24)
|
||||
|
||||
#define CCR1_MASK_CTSE BIT(0)
|
||||
#define CCR1_MASK_SPB2DT BIT(4)
|
||||
#define CCR1_MASK_SPB2IO BIT(5)
|
||||
#define CCR1_MASK_PE BIT(8)
|
||||
#define CCR1_MASK_PM BIT(9)
|
||||
#define CCR1_MASK_NFEN BIT(28)
|
||||
|
||||
#define CCR2_MASK_BGDM BIT(4)
|
||||
#define CCR2_MASK_ABCS BIT(5)
|
||||
#define CCR2_MASK_ABCSE BIT(6)
|
||||
#define CCR2_MASK_BRR GENMASK(15, 8)
|
||||
#define CCR2_MASK_BRME BIT(16)
|
||||
#define CCR2_MASK_CKS GENMASK(21, 20)
|
||||
#define CCR2_MASK_MDDR GENMASK(31, 24)
|
||||
#define CCR2_MASK_BAUD_SETTING \
|
||||
(CCR2_MASK_BRME | CCR2_MASK_ABCSE | CCR2_MASK_ABCS | CCR2_MASK_BGDM | CCR2_MASK_CKS | \
|
||||
CCR2_MASK_BRR | CCR2_MASK_MDDR)
|
||||
|
||||
#define CCR3_MASK_STP BIT(14)
|
||||
#define CCR3_MASK_MP BIT(19)
|
||||
#define CCR3_MASK_FM BIT(20)
|
||||
#define CCR3_MASK_CKE (BIT(24) | BIT(25))
|
||||
#define CCR3_CKE_ENABLE BIT(24)
|
||||
#define CCR3_CHR_7BIT (BIT(8) | BIT(9))
|
||||
#define CCR3_CHR_8BIT BIT(9)
|
||||
|
||||
#define CCR4_MASK_ASEN BIT(16)
|
||||
#define CCR4_MASK_ATEN BIT(17)
|
||||
|
||||
#define FCR_MASK_TFRST BIT(15)
|
||||
#define FCR_MASK_RFRST BIT(23)
|
||||
#define FCR_MASK_TTRG GENMASK(12, 8)
|
||||
#define FCR_MASK_RTRG GENMASK(20, 16)
|
||||
#define FCR_TTRG_15 (15 << 8)
|
||||
#define FCR_RTRG_15 (15 << 16)
|
||||
|
||||
#define CSR_MASK_ORER BIT(24)
|
||||
#define CSR_MASK_PER BIT(27)
|
||||
#define CSR_MASK_FER BIT(28)
|
||||
#define CSR_MASK_TDRE BIT(29)
|
||||
#define CSR_MASK_TEND BIT(30)
|
||||
#define CSR_MASK_RDRF BIT(31)
|
||||
|
||||
#define FRSR_MASK_DR BIT(0)
|
||||
#define FRSR_R(val) ((val >> 7) & 0x3f)
|
||||
|
||||
#define FTSR_T(val) (val & 0x3f)
|
||||
|
||||
#define CFCLR_MASK_ERSC BIT(4)
|
||||
#define CFCLR_MASK_DCMFC BIT(16)
|
||||
#define CFCLR_MASK_DPERC BIT(17)
|
||||
#define CFCLR_MASK_DFERC BIT(18)
|
||||
#define CFCLR_MASK_ORERC BIT(24)
|
||||
#define CFCLR_MASK_MFFC BIT(26)
|
||||
#define CFCLR_MASK_PERC BIT(27)
|
||||
#define CFCLR_MASK_FERC BIT(28)
|
||||
#define CFCLR_MASK_TDREC BIT(29)
|
||||
#define CFCLR_MASK_RDRFC BIT(31)
|
||||
#define CFCLR_ALL_FLAG_CLEAR \
|
||||
(CFCLR_MASK_ERSC | CFCLR_MASK_DCMFC | CFCLR_MASK_DPERC | CFCLR_MASK_DFERC | \
|
||||
CFCLR_MASK_ORERC | CFCLR_MASK_MFFC | CFCLR_MASK_PERC | CFCLR_MASK_FERC | \
|
||||
CFCLR_MASK_TDREC | CFCLR_MASK_RDRFC)
|
||||
|
||||
#define FFCLR_MASK_DRC BIT(0)
|
||||
|
||||
#define MSTPCRA (volatile uint32_t *)(0x80280000 + 0x300)
|
||||
#define MSTPCRA_MASK_SCIx(x) BIT(x + 8)
|
||||
#define BASE_TO_IFACE_ID(base) ((base & 0x1000000) ? 5 : ((base & 0xff00) >> 10) - 4)
|
||||
|
||||
#define CCR2_MDDR_128 BIT(31)
|
||||
#define CCR2_CKS_0 0
|
||||
#define CCR2_BRME_0 0
|
||||
#define CCR2_BRR_243 (0xf3 << 8)
|
||||
#define CCR2_BRR_39 (0x27 << 8)
|
||||
#define CCR2_BGDM_1 BIT(4)
|
||||
|
||||
#define CCR2_BAUD_SETTING_9600 (CCR2_MDDR_128 | CCR2_BRR_243)
|
||||
#define CCR2_BAUD_SETTING_115200 (CCR2_MDDR_128 | CCR2_BRR_39 | CCR2_BGDM_1)
|
||||
|
||||
#endif /* ZEPHYR_DRIVERS_SERIAL_UART_RZT2M_H_ */
|
||||
|
|
@ -88,5 +88,30 @@
|
|||
reg = <0x81281a00 0x10>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
uart0: serial@80001000 {
|
||||
compatible = "renesas,rzt2m-uart";
|
||||
reg = <0x80001000 0x1000>;
|
||||
current-speed = <115200>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
|
||||
<GIC_SPI 289 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
|
||||
<GIC_SPI 290 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
|
||||
<GIC_SPI 291 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-names = "rx_err", "rx", "tx", "tx_end";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@80001c00 {
|
||||
compatible = "renesas,rzt2m-uart";
|
||||
reg = <0x80001c00 0x1000>;
|
||||
current-speed = <115200>;
|
||||
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
|
||||
<GIC_SPI 301 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
|
||||
<GIC_SPI 302 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
|
||||
<GIC_SPI 303 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-names = "rx_err", "rx", "tx", "tx_end";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
|
|
|||
26
dts/bindings/serial/renesas,rzt2m-uart.yaml
Normal file
26
dts/bindings/serial/renesas,rzt2m-uart.yaml
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
# Copyright (c) 2023 Antmicro <www.antmicro.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Renesas RZ/T2M UART
|
||||
|
||||
compatible: "renesas,rzt2m-uart"
|
||||
|
||||
include:
|
||||
- name: uart-controller.yaml
|
||||
- name: pinctrl-device.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
current-speed:
|
||||
required: true
|
||||
description: |
|
||||
Initial baud rate setting for UART. Only a fixed set of baud
|
||||
rates is currently supported.
|
||||
enum:
|
||||
- 9600
|
||||
- 115200
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
Loading…
Reference in a new issue