soc: arm: stm32h7RS introduce stm32h7R/h7S devices

Add the new STM32HRSX serie with stm32H7R3, stm32H7R7,
stm32H7S3, stm32H7S7 devices from STMicroelectronics
Same MPU regions as stm32h7 device.

Signed-off-by: Francois Ramu <francois.ramu@st.com>

soc/st/stm32/soc.yml

@@ -102,6 +102,12 @@ family:
     - name: stm32h562xx
     - name: stm32h563xx
     - name: stm32h573xx
+  - name: stm32h7rsx
+    socs:
+    - name: stm32h7r3xx
+    - name: stm32h7r7xx
+    - name: stm32h7s3xx
+    - name: stm32h7s7xx
   - name: stm32h7x
     socs:
     - name: stm32h7a3xx

soc/st/stm32/stm32h7rsx/CMakeLists.txt

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/st/stm32/stm32h7rsx/Kconfig

@@ -0,0 +1,16 @@
+# STMicroelectronics STM32H7RS MCU series
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32H7RSX
+	select ARM
+	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select HAS_STM32CUBE
+	select CPU_HAS_ARM_MPU
+	select HAS_SWO
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select CPU_HAS_ICACHE
+	select CPU_HAS_DCACHE

soc/st/stm32/stm32h7rsx/Kconfig.defconfig

@@ -0,0 +1,16 @@
+# ST Microelectronics STM32H7RS MCU line
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+# Kconfig symbols common to STM32H7RS series
+
+if SOC_SERIES_STM32H7RSX
+
+rsource "Kconfig.defconfig.stm32h7*"
+
+config ROM_START_OFFSET
+	default 0x400 if BOOTLOADER_MCUBOOT
+	default 0x0   if !BOOTLOADER_MCUBOOT
+
+endif # SOC_SERIES_STM32H7RSX

soc/st/stm32/stm32h7rsx/Kconfig.defconfig.stm32h7r3xx

@@ -0,0 +1,11 @@
+# ST STM32H7R3X MCU configuration options
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32H7R3XX
+
+config NUM_IRQS
+	default 156
+
+endif # SOC_STM32H7R3XX

soc/st/stm32/stm32h7rsx/Kconfig.defconfig.stm32h7r7xx

@@ -0,0 +1,11 @@
+# ST STM32H7R7X MCU configuration options
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32H7R7XX
+
+config NUM_IRQS
+	default 156
+
+endif # SOC_STM32H7R7XX

soc/st/stm32/stm32h7rsx/Kconfig.defconfig.stm32h7s3xx

@@ -0,0 +1,11 @@
+# ST STM32H7S3X MCU configuration options
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32H7S3XX
+
+config NUM_IRQS
+	default 156
+
+endif # SOC_STM32H7S3XX

soc/st/stm32/stm32h7rsx/Kconfig.defconfig.stm32h7s7xx

@@ -0,0 +1,11 @@
+# ST STM32H7S7X MCU configuration options
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32H7S7XX
+
+config NUM_IRQS
+	default 156
+
+endif # SOC_STM32H7S7XX

soc/st/stm32/stm32h7rsx/Kconfig.soc

@@ -0,0 +1,33 @@
+# ST Microelectronics STM32H7RS MCU line
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32H7RSX
+	bool
+	select SOC_FAMILY_STM32
+
+config SOC_SERIES
+	default "stm32h7rsx" if SOC_SERIES_STM32H7RSX
+
+config SOC_STM32H7R3XX
+	bool
+	select SOC_SERIES_STM32H7RSX
+
+config SOC_STM32H7R7XX
+	bool
+	select SOC_SERIES_STM32H7RSX
+
+config SOC_STM32H7S3XX
+	bool
+	select SOC_SERIES_STM32H7RSX
+
+config SOC_STM32H7S7XX
+	bool
+	select SOC_SERIES_STM32H7RSX
+
+config SOC
+	default "stm32h7r3xx" if SOC_STM32H7R3XX
+	default "stm32h7r7xx" if SOC_STM32H7R7XX
+	default "stm32h7s3xx" if SOC_STM32H7S3XX
+	default "stm32h7s7xx" if SOC_STM32H7S7XX

soc/st/stm32/stm32h7rsx/soc.c

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32H7RS CM7 processor
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/cache.h>
+#include <soc.h>
+#include <stm32_ll_bus.h>
+#include <stm32_ll_pwr.h>
+#include <stm32_ll_rcc.h>
+
+#include <cmsis_core.h>
+
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int stm32h7rs_init(void)
+{
+	sys_cache_instr_enable();
+	sys_cache_data_enable();
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	/* At reset, system core clock is set to 64 MHz from HSI */
+	SystemCoreClock = 64000000;
+
+	/* Power Configuration */
+#if !defined(SMPS) && \
+		(defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS) || \
+		defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO) || \
+		defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO) || \
+		defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
+		defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
+		defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT) || \
+		defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT))
+#error Unsupported configuration: Selected SoC do not support SMPS
+#endif
+#if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
+	LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
+#elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
+#elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
+#elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
+#elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
+#elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
+#elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
+	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
+#elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
+	LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
+#else
+	LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
+#endif
+	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
+	while (LL_PWR_IsActiveFlag_VOSRDY() == 0) {
+	}
+
+	return 0;
+}
+
+SYS_INIT(stm32h7rs_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32h7rsx/soc.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32H7RS_SOC_H_
+#define _STM32H7RS_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <stm32h7rsxx.h>
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32H7RS_SOC_H_ */