drivers: spi: stm32 half duplex support
Add support for SPI_HALF_DUPLEX flag for STM32 SPI driver Signed-off-by: Riku Karjalainen <riku.karjalainen@vaisala.com>
This commit is contained in:
Riku Karjalainen
Benjamin Cabé
parent
9b194e1d33
commit
5011ebad3b
1 changed files with 281 additions and 46 deletions
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@ -274,23 +274,35 @@ static int spi_stm32_dma_rx_load(const struct device *dev, uint8_t *buf,
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return dma_start(data->dma_rx.dma_dev, data->dma_rx.channel);
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}
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static int spi_dma_move_buffers(const struct device *dev, size_t len)
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static int spi_dma_move_rx_buffers(const struct device *dev, size_t len)
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{
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struct spi_stm32_data *data = dev->data;
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int ret;
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size_t dma_segment_len;
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dma_segment_len = len * data->dma_rx.dma_cfg.dest_data_size;
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ret = spi_stm32_dma_rx_load(dev, data->ctx.rx_buf, dma_segment_len);
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return spi_stm32_dma_rx_load(dev, data->ctx.rx_buf, dma_segment_len);
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}
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static int spi_dma_move_tx_buffers(const struct device *dev, size_t len)
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{
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struct spi_stm32_data *data = dev->data;
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size_t dma_segment_len;
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dma_segment_len = len * data->dma_tx.dma_cfg.source_data_size;
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return spi_stm32_dma_tx_load(dev, data->ctx.tx_buf, dma_segment_len);
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}
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static int spi_dma_move_buffers(const struct device *dev, size_t len)
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{
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int ret;
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ret = spi_dma_move_rx_buffers(dev, len);
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if (ret != 0) {
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return ret;
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}
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dma_segment_len = len * data->dma_tx.dma_cfg.source_data_size;
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ret = spi_stm32_dma_tx_load(dev, data->ctx.tx_buf, dma_segment_len);
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return ret;
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return spi_dma_move_tx_buffers(dev, len);
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}
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#endif /* CONFIG_SPI_STM32_DMA */
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@ -366,11 +378,15 @@ static int spi_stm32_get_err(SPI_TypeDef *spi)
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static void spi_stm32_shift_fifo(SPI_TypeDef *spi, struct spi_stm32_data *data)
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{
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if (ll_func_rx_is_not_empty(spi)) {
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uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);
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if (transfer_dir != LL_SPI_HALF_DUPLEX_TX &&
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ll_func_rx_is_not_empty(spi)) {
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spi_stm32_read_next_frame(spi, data);
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}
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if (ll_func_tx_is_not_full(spi)) {
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if (transfer_dir != LL_SPI_HALF_DUPLEX_RX &&
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ll_func_tx_is_not_full(spi)) {
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spi_stm32_send_next_frame(spi, data);
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}
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}
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@ -382,17 +398,23 @@ static void spi_stm32_shift_m(const struct spi_stm32_config *cfg,
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if (cfg->fifo_enabled) {
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spi_stm32_shift_fifo(cfg->spi, data);
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} else {
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while (!ll_func_tx_is_not_full(cfg->spi)) {
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/* NOP */
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uint32_t transfer_dir = LL_SPI_GetTransferDirection(cfg->spi);
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if (transfer_dir != LL_SPI_HALF_DUPLEX_RX) {
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while (!ll_func_tx_is_not_full(cfg->spi)) {
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/* NOP */
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}
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spi_stm32_send_next_frame(cfg->spi, data);
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}
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spi_stm32_send_next_frame(cfg->spi, data);
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if (transfer_dir != LL_SPI_HALF_DUPLEX_TX) {
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while (!ll_func_rx_is_not_empty(cfg->spi)) {
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/* NOP */
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}
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while (!ll_func_rx_is_not_empty(cfg->spi)) {
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/* NOP */
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spi_stm32_read_next_frame(cfg->spi, data);
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}
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spi_stm32_read_next_frame(cfg->spi, data);
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}
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}
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@ -511,11 +533,15 @@ static void spi_stm32_complete(const struct device *dev, int status)
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}
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
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uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);
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if (cfg->fifo_enabled) {
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LL_SPI_ClearFlag_TXTF(spi);
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LL_SPI_ClearFlag_OVR(spi);
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LL_SPI_ClearFlag_EOT(spi);
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LL_SPI_SetTransferSize(spi, 0);
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} else if (transfer_dir == LL_SPI_HALF_DUPLEX_RX) {
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LL_SPI_SetTransferSize(spi, 0);
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) */
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@ -557,14 +583,31 @@ static void spi_stm32_isr(const struct device *dev)
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err = spi_stm32_shift_frames(cfg, data);
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}
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if (err || !spi_stm32_transfer_ongoing(data)) {
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if (err) {
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spi_stm32_complete(dev, err);
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}
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uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);
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if (transfer_dir == LL_SPI_FULL_DUPLEX) {
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if (!spi_stm32_transfer_ongoing(data)) {
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spi_stm32_complete(dev, err);
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}
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} else if (transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
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if (!spi_context_tx_on(&data->ctx)) {
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spi_stm32_complete(dev, err);
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}
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} else {
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if (!spi_context_rx_on(&data->ctx)) {
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spi_stm32_complete(dev, err);
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}
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}
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}
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#endif /* CONFIG_SPI_STM32_INTERRUPT */
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static int spi_stm32_configure(const struct device *dev,
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const struct spi_config *config)
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const struct spi_config *config,
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bool write)
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{
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const struct spi_stm32_config *cfg = dev->config;
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struct spi_stm32_data *data = dev->data;
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@ -583,7 +626,13 @@ static int spi_stm32_configure(const struct device *dev,
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int br;
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if (spi_context_configured(&data->ctx, config)) {
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/* Nothing to do */
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if (config->operation & SPI_HALF_DUPLEX) {
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if (write) {
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LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_TX);
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} else {
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LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_RX);
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}
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}
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return 0;
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}
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@ -652,7 +701,15 @@ static int spi_stm32_configure(const struct device *dev,
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LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_1EDGE);
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}
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LL_SPI_SetTransferDirection(spi, LL_SPI_FULL_DUPLEX);
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if (config->operation & SPI_HALF_DUPLEX) {
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if (write) {
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LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_TX);
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} else {
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LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_RX);
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}
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} else {
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LL_SPI_SetTransferDirection(spi, LL_SPI_FULL_DUPLEX);
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}
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if (config->operation & SPI_TRANSFER_LSB) {
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LL_SPI_SetTransferBitOrder(spi, LL_SPI_LSB_FIRST);
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@ -744,7 +801,14 @@ static int32_t spi_stm32_count_bufset_frames(const struct spi_config *config,
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if ((num_bytes % bytes_per_frame) != 0) {
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return -EINVAL;
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}
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return num_bytes / bytes_per_frame;
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int frames = num_bytes / bytes_per_frame;
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if (frames > UINT16_MAX) {
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return -EMSGSIZE;
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}
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return frames;
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}
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static int32_t spi_stm32_count_total_frames(const struct spi_config *config,
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@ -763,14 +827,80 @@ static int32_t spi_stm32_count_total_frames(const struct spi_config *config,
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return rx_frames;
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}
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if (tx_frames > UINT16_MAX || rx_frames > UINT16_MAX) {
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return -EMSGSIZE;
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}
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return MAX(rx_frames, tx_frames);
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) */
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static int spi_stm32_half_duplex_switch_to_receive(const struct spi_stm32_config *cfg,
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struct spi_stm32_data *data)
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{
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SPI_TypeDef *spi = cfg->spi;
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if (!spi_context_tx_on(&data->ctx) &&
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spi_context_rx_on(&data->ctx)) {
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#ifndef CONFIG_SPI_STM32_INTERRUPT
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while (ll_func_spi_is_busy(spi)) {
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/* NOP */
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}
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LL_SPI_Disable(spi);
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#endif /* CONFIG_SPI_STM32_INTERRUPT*/
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
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const struct spi_config *config = data->ctx.config;
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if (SPI_OP_MODE_GET(config->operation) == SPI_OP_MODE_MASTER) {
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int num_bytes = spi_context_total_rx_len(&data->ctx);
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uint8_t bytes_per_frame = SPI_WORD_SIZE_GET(config->operation) / 8;
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if ((num_bytes % bytes_per_frame) != 0) {
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return -EINVAL;
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}
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LL_SPI_SetTransferSize(spi, (uint32_t) num_bytes / bytes_per_frame);
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) */
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LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_RX);
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LL_SPI_Enable(spi);
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
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/* With the STM32MP1, STM32U5 and the STM32H7,
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* if the device is the SPI master,
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* we need to enable the start of the transfer with
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* LL_SPI_StartMasterTransfer(spi).
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*/
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if (LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {
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LL_SPI_StartMasterTransfer(spi);
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while (!LL_SPI_IsActiveMasterTransfer(spi)) {
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/* NOP */
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}
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) */
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#if CONFIG_SOC_SERIES_STM32H7X
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/*
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* Add a small delay after enabling to prevent transfer stalling at high
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* system clock frequency (see errata sheet ES0392).
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*/
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k_busy_wait(WAIT_1US);
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#endif
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#ifdef CONFIG_SPI_STM32_INTERRUPT
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
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if (cfg->fifo_enabled) {
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LL_SPI_EnableIT_EOT(spi);
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) */
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ll_func_enable_int_errors(spi);
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ll_func_enable_int_rx_not_empty(spi);
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#endif /* CONFIG_SPI_STM32_INTERRUPT */
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}
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return 0;
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}
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static int transceive(const struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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@ -798,7 +928,7 @@ static int transceive(const struct device *dev,
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spi_stm32_pm_policy_state_lock_get(dev);
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ret = spi_stm32_configure(dev, config);
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ret = spi_stm32_configure(dev, config, tx_bufs != NULL);
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if (ret) {
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goto end;
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}
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@ -810,10 +940,23 @@ static int transceive(const struct device *dev,
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 2);
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}
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uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
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if (cfg->fifo_enabled && SPI_OP_MODE_GET(config->operation) == SPI_OP_MODE_MASTER) {
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int total_frames = spi_stm32_count_total_frames(
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config, tx_bufs, rx_bufs);
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int total_frames;
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if (transfer_dir == LL_SPI_FULL_DUPLEX) {
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total_frames = spi_stm32_count_total_frames(
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config, tx_bufs, rx_bufs);
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} else if (transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
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total_frames = spi_stm32_count_bufset_frames(
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config, tx_bufs);
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} else {
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total_frames = spi_stm32_count_bufset_frames(
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config, rx_bufs);
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}
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if (total_frames < 0) {
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ret = total_frames;
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goto end;
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@ -866,10 +1009,24 @@ static int transceive(const struct device *dev,
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ll_func_enable_int_tx_empty(spi);
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ret = spi_context_wait_for_completion(&data->ctx);
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do {
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ret = spi_context_wait_for_completion(&data->ctx);
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if (!ret &&
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transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
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ret = spi_stm32_half_duplex_switch_to_receive(cfg, data);
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transfer_dir = LL_SPI_GetTransferDirection(spi);
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}
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} while (!ret && spi_stm32_transfer_ongoing(data));
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#else /* CONFIG_SPI_STM32_INTERRUPT */
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do {
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ret = spi_stm32_shift_frames(cfg, data);
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if (!ret &&
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transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
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ret = spi_stm32_half_duplex_switch_to_receive(cfg, data);
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transfer_dir = LL_SPI_GetTransferDirection(spi);
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}
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} while (!ret && spi_stm32_transfer_ongoing(data));
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spi_stm32_complete(dev, ret);
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@ -999,11 +1156,26 @@ static int transceive_dma(const struct device *dev,
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k_sem_reset(&data->status_sem);
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ret = spi_stm32_configure(dev, config);
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ret = spi_stm32_configure(dev, config, tx_bufs != NULL);
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if (ret) {
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goto end;
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}
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uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
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if (transfer_dir == LL_SPI_HALF_DUPLEX_RX) {
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int frames = spi_stm32_count_bufset_frames(config, rx_bufs);
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if (frames < 0) {
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ret = frames;
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goto end;
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}
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LL_SPI_SetTransferSize(cfg->spi, frames);
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}
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#endif /* st_stm32h7_spi */
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/* Set buffers info */
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if (SPI_WORD_SIZE_GET(config->operation) == 8) {
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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@ -1013,11 +1185,22 @@ static int transceive_dma(const struct device *dev,
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
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/* set request before enabling (else SPI CFG1 reg is write protected) */
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LL_SPI_EnableDMAReq_RX(spi);
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LL_SPI_EnableDMAReq_TX(spi);
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if (transfer_dir == LL_SPI_FULL_DUPLEX) {
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LL_SPI_EnableDMAReq_RX(spi);
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LL_SPI_EnableDMAReq_TX(spi);
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} else if (transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
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LL_SPI_EnableDMAReq_TX(spi);
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} else {
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LL_SPI_EnableDMAReq_RX(spi);
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}
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LL_SPI_Enable(spi);
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if (LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {
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/* In half-duplex rx mode, start transfer after
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* setting DMA configurations
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*/
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if (transfer_dir != LL_SPI_HALF_DUPLEX_RX &&
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LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {
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LL_SPI_StartMasterTransfer(spi);
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}
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#else
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@ -1030,17 +1213,33 @@ static int transceive_dma(const struct device *dev,
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while (data->ctx.rx_len > 0 || data->ctx.tx_len > 0) {
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size_t dma_len;
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if (data->ctx.rx_len == 0) {
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dma_len = data->ctx.tx_len;
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} else if (data->ctx.tx_len == 0) {
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dma_len = data->ctx.rx_len;
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} else {
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dma_len = MIN(data->ctx.tx_len, data->ctx.rx_len);
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}
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data->status_flags = 0;
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ret = spi_dma_move_buffers(dev, dma_len);
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if (transfer_dir == LL_SPI_FULL_DUPLEX) {
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if (data->ctx.rx_len == 0) {
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dma_len = data->ctx.tx_len;
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} else if (data->ctx.tx_len == 0) {
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dma_len = data->ctx.rx_len;
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} else {
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dma_len = MIN(data->ctx.tx_len, data->ctx.rx_len);
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}
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ret = spi_dma_move_buffers(dev, dma_len);
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} else if (transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
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dma_len = data->ctx.tx_len;
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ret = spi_dma_move_tx_buffers(dev, dma_len);
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} else {
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dma_len = data->ctx.rx_len;
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ret = spi_dma_move_rx_buffers(dev, dma_len);
|
||||
}
|
||||
|
||||
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
|
||||
if (transfer_dir == LL_SPI_HALF_DUPLEX_RX &&
|
||||
LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {
|
||||
LL_SPI_StartMasterTransfer(spi);
|
||||
}
|
||||
#endif /* st_stm32h7_spi */
|
||||
|
||||
if (ret != 0) {
|
||||
break;
|
||||
}
|
||||
|
|
@ -1048,8 +1247,14 @@ static int transceive_dma(const struct device *dev,
|
|||
#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
|
||||
|
||||
/* toggle the DMA request to restart the transfer */
|
||||
LL_SPI_EnableDMAReq_RX(spi);
|
||||
LL_SPI_EnableDMAReq_TX(spi);
|
||||
if (transfer_dir == LL_SPI_FULL_DUPLEX) {
|
||||
LL_SPI_EnableDMAReq_RX(spi);
|
||||
LL_SPI_EnableDMAReq_TX(spi);
|
||||
} else if (transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
|
||||
LL_SPI_EnableDMAReq_TX(spi);
|
||||
} else {
|
||||
LL_SPI_EnableDMAReq_RX(spi);
|
||||
}
|
||||
#endif /* ! st_stm32h7_spi */
|
||||
|
||||
ret = wait_dma_rx_tx_done(dev);
|
||||
|
|
@ -1081,8 +1286,38 @@ static int transceive_dma(const struct device *dev,
|
|||
uint8_t frame_size_bytes = bits2bytes(
|
||||
SPI_WORD_SIZE_GET(config->operation));
|
||||
|
||||
spi_context_update_tx(&data->ctx, frame_size_bytes, dma_len);
|
||||
spi_context_update_rx(&data->ctx, frame_size_bytes, dma_len);
|
||||
if (transfer_dir == LL_SPI_FULL_DUPLEX) {
|
||||
spi_context_update_tx(&data->ctx, frame_size_bytes, dma_len);
|
||||
spi_context_update_rx(&data->ctx, frame_size_bytes, dma_len);
|
||||
} else if (transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
|
||||
spi_context_update_tx(&data->ctx, frame_size_bytes, dma_len);
|
||||
} else {
|
||||
spi_context_update_rx(&data->ctx, frame_size_bytes, dma_len);
|
||||
}
|
||||
|
||||
if (transfer_dir == LL_SPI_HALF_DUPLEX_TX &&
|
||||
!spi_context_tx_on(&data->ctx) &&
|
||||
spi_context_rx_on(&data->ctx)) {
|
||||
LL_SPI_Disable(spi);
|
||||
LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_RX);
|
||||
|
||||
transfer_dir = LL_SPI_HALF_DUPLEX_RX;
|
||||
|
||||
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
|
||||
int frames = spi_stm32_count_bufset_frames(config, rx_bufs);
|
||||
|
||||
if (frames < 0) {
|
||||
ret = frames;
|
||||
break;
|
||||
}
|
||||
|
||||
LL_SPI_SetTransferSize(cfg->spi, frames);
|
||||
|
||||
LL_SPI_EnableDMAReq_RX(spi);
|
||||
#endif /* st_stm32h7_spi */
|
||||
|
||||
LL_SPI_Enable(spi);
|
||||
}
|
||||
}
|
||||
|
||||
/* spi complete relies on SPI Status Reg which cannot be disabled */
|
||||
|
|
|
|||
Loading…
Reference in a new issue