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boards: silabs: removed FLASH_BASE_ADDRESS

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Removed FLASH_BASE_ADDRESS configuration from various boards' Kconfig.
The only thing needed in order to do this was to update the relevant dtsi
files so that the flash0 node has its reg property configured properly.

Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
This commit is contained in:
Yishai Jaffe 2024-12-18 14:21:38 +02:00 committed by Benjamin Cabé
parent ab9af6f161
commit 503721bbcc
13 changed files with 13 additions and 55 deletions
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4
boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig
View file

@ -9,10 +9,6 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
config FLASH_BASE_ADDRESS
hex
default 0x08000000
if SOC_GECKO_USE_RAIL
config FPU

4
boards/silabs/radio_boards/slwrb4104a/Kconfig.defconfig
View file

@ -10,10 +10,6 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
config FLASH_BASE_ADDRESS
hex
default 0x0
config LOG_BACKEND_SWO_FREQ_HZ
default 875000
depends on LOG_BACKEND_SWO

4
boards/silabs/radio_boards/slwrb4161a/Kconfig.defconfig
View file

@ -10,10 +10,6 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
config FLASH_BASE_ADDRESS
hex
default 0x0
config LOG_BACKEND_SWO_FREQ_HZ
default 875000
depends on LOG_BACKEND_SWO

4
boards/silabs/radio_boards/slwrb4170a/Kconfig.defconfig
View file

@ -10,10 +10,6 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
config FLASH_BASE_ADDRESS
hex
default 0x0
config LOG_BACKEND_SWO_FREQ_HZ
default 875000
depends on LOG_BACKEND_SWO

4
boards/silabs/radio_boards/slwrb4180a/Kconfig.defconfig
View file

@ -10,10 +10,6 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
config FLASH_BASE_ADDRESS
hex
default 0x0
config LOG_BACKEND_SWO_FREQ_HZ
default 875000
depends on LOG_BACKEND_SWO

4
boards/silabs/radio_boards/slwrb4250b/Kconfig.defconfig
View file

@ -10,10 +10,6 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
config FLASH_BASE_ADDRESS
hex
default 0x0
config LOG_BACKEND_SWO_FREQ_HZ
default 875000
depends on LOG_BACKEND_SWO

4
boards/silabs/radio_boards/slwrb4255a/Kconfig.defconfig
View file

@ -10,10 +10,6 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
config FLASH_BASE_ADDRESS
hex
default 0x0
config LOG_BACKEND_SWO_FREQ_HZ
default 875000
depends on LOG_BACKEND_SWO

4
boards/silabs/radio_boards/xg24_rb4187c/Kconfig.defconfig
View file

@ -10,10 +10,6 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
config FLASH_BASE_ADDRESS
hex
default 0x08000000
config LOG_BACKEND_SWO_FREQ_HZ
default 875000
depends on LOG_BACKEND_SWO

4
boards/sparkfun/thing_plus_matter_mgm240p/Kconfig.defconfig
View file

@ -12,10 +12,6 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
config FLASH_BASE_ADDRESS
hex
default 0x08000000
if SOC_GECKO_USE_RAIL
config FPU

2
dts/arm/silabs/efr32mg24.dtsi
View file

@ -268,7 +268,7 @@
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
flash0: flash@8000000 {
compatible = "soc-nv-flash";
write-block-size = <4>;
erase-block-size = <8192>;

10
dts/arm/silabs/efr32mg24b020f1536im40.dtsi
View file

@ -16,11 +16,9 @@
compatible = "silabs,efr32mg24b020f1536im40",
"silabs,efr32mg24", "silabs,efr32",
"simple-bus";
flash-controller@50030000 {
flash0: flash@0 {
reg = <0 DT_SIZE_K(1536)>;
};
};
};
};
&flash0 {
reg = <0x08000000 DT_SIZE_K(1536)>;
};

10
dts/arm/silabs/efr32mg24b220f1536im48.dtsi
View file

@ -16,11 +16,9 @@
compatible = "silabs,efr32mg24b220f1536im48",
"silabs,efr32mg24", "silabs,efr32",
"simple-bus";
flash-controller@50030000 {
flash0: flash@0 {
reg = <0 DT_SIZE_K(1536)>;
};
};
};
};
&flash0 {
reg = <0x08000000 DT_SIZE_K(1536)>;
};

10
dts/arm/silabs/efr32mg24b310f1536im48.dtsi
View file

@ -16,11 +16,9 @@
compatible = "silabs,efr32mg24b310f1536im48",
"silabs,efr32mg24", "silabs,efr32",
"simple-bus";
flash-controller@50030000 {
flash0: flash@0 {
reg = <0 DT_SIZE_K(1536)>;
};
};
};
};
&flash0 {
reg = <0x08000000 DT_SIZE_K(1536)>;
};