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arch: arm: cortex_a_r: Set XPSR endianness bit

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When this bit is not set, it defaults to 0 (little endian). This
causes issues for big-endian devices, as data will be accessed using
little endian.

Signed-off-by: Sigmund Klåpbakken <sigmundklaa@outlook.com>
This commit is contained in:
Sigmund Klåpbakken 2024-05-15 12:39:31 +02:00 committed by Anas Nashif
parent fb53d2ef8d
commit 5100f1185d
2 changed files with 5 additions and 0 deletions
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4
arch/arm/core/cortex_a_r/thread.c
View file

@ -95,6 +95,10 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
iframe->a4 = (uint32_t)p3; iframe->a4 = (uint32_t)p3;
iframe->xpsr = A_BIT | MODE_SYS; iframe->xpsr = A_BIT | MODE_SYS;
#if defined(CONFIG_BIG_ENDIAN)
iframe->xpsr |= E_BIT;
#endif /* CONFIG_BIG_ENDIAN */
#if defined(CONFIG_COMPILER_ISA_THUMB2) #if defined(CONFIG_COMPILER_ISA_THUMB2)
iframe->xpsr |= T_BIT; iframe->xpsr |= T_BIT;
#endif /* CONFIG_COMPILER_ISA_THUMB2 */ #endif /* CONFIG_COMPILER_ISA_THUMB2 */

1
include/zephyr/arch/arm/cortex_a_r/cpu.h
View file

@ -26,6 +26,7 @@
#define MODE_SYS 0x1f #define MODE_SYS 0x1f
#define MODE_MASK 0x1f #define MODE_MASK 0x1f
#define E_BIT (1 << 9)
#define A_BIT (1 << 8) #define A_BIT (1 << 8)
#define I_BIT (1 << 7) #define I_BIT (1 << 7)
#define F_BIT (1 << 6) #define F_BIT (1 << 6)