soc: stm32: Add support for the stm32h755

Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.

Signed-off-by: Mike Banducci <michael.banducci@sandc.com>

drivers/clock_control/clock_stm32_ll_h7.c

@@ -109,7 +109,8 @@
 	defined(CONFIG_SOC_STM32H745XX_M7) || defined(CONFIG_SOC_STM32H745XX_M4) ||\
 	defined(CONFIG_SOC_STM32H747XX_M7) || defined(CONFIG_SOC_STM32H747XX_M4) ||\
 	defined(CONFIG_SOC_STM32H750XX) ||\
-	defined(CONFIG_SOC_STM32H753XX)
+	defined(CONFIG_SOC_STM32H753XX) ||\
+	defined(CONFIG_SOC_STM32H755XX_M7) || defined(CONFIG_SOC_STM32H755XX_M4)
 /* All h7 SoC with maximum 480MHz SYSCLK */
 #define SYSCLK_FREQ_MAX		480000000UL
 #define AHB_FREQ_MAX		240000000UL

dts/arm/st/h7/stm32h755.dtsi

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h7_dualcore.dtsi>
+#include <st/h7/stm32h745.dtsi>
+
+/ {
+	soc {
+		compatible = "st,stm32h755", "st,stm32h7", "simple-bus";
+
+		cryp: cryp@48021000 {
+			compatible = "st,stm32-cryp";
+			reg = <0x48021000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+			interrupts = <79 0>;
+			status = "disabled";
+		};
+
+		hash: cryp@48021400 {
+			compatible = "st,stm32-cryp";
+			reg = <0x48021400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
+			interrupts = <80 0>;
+			status = "disabled";
+		};
+	};
+};

dts/arm/st/h7/stm32h755Xi_m4.dtsi

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h755.dtsi>
+
+/delete-node/ &flash0;
+
+/ {
+	cpus {
+		/delete-node/ cpu@0;
+	};
+
+	soc {
+		flash-controller@52002000 {
+			flash1: flash@8100000 {
+				reg = <0x08100000 DT_SIZE_K(1024)>;
+			};
+		};
+
+		mailbox@58026400 {
+			interrupts = <126 0>;
+		};
+	};
+};

dts/arm/st/h7/stm32h755Xi_m7.dtsi

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024 S&C Electric Company <Michael.Banducci@sandc.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h755.dtsi>
+
+/delete-node/ &flash1;
+
+/ {
+	cpus {
+		/delete-node/ cpu@1;
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "zephyr,memory-region", "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+
+		mailbox@58026400 {
+			interrupts = <125 0>;
+		};
+	};
+};

soc/st/stm32/soc.yml

@@ -128,6 +128,10 @@ family:
       - name: m4
     - name: stm32h750xx
     - name: stm32h753xx
+    - name: stm32h755xx
+      cpuclusters:
+      - name: m7
+      - name: m4
   - name: stm32l0x
     socs:
     - name: stm32l010x4

soc/st/stm32/stm32h7x/Kconfig

@@ -52,6 +52,12 @@ config SOC_STM32H750XX
 config SOC_STM32H753XX
 	select CPU_CORTEX_M7
 
+config SOC_STM32H755XX_M7
+	select CPU_CORTEX_M7
+
+config SOC_STM32H755XX_M4
+	select CPU_CORTEX_M4
+
 config SOC_STM32H7A3XX
 	select CPU_CORTEX_M7
 

soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h755xx

@@ -0,0 +1,14 @@
+# ST STM32H755X MCU configuration options
+
+# Copyright (c) 2024 S&C Electric Company
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32H755XX_M7 || SOC_STM32H755XX_M4
+
+config STM32H7_DUAL_CORE
+	default y
+
+config NUM_IRQS
+	default 150
+
+endif # SOC_STM32H755XX_M7 || SOC_STM32H755XX_M4

soc/st/stm32/stm32h7x/Kconfig.soc

@@ -60,6 +60,14 @@ config SOC_STM32H753XX
 	bool
 	select SOC_SERIES_STM32H7X
 
+config SOC_STM32H755XX_M4
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H755XX_M7
+	bool
+	select SOC_SERIES_STM32H7X
+
 config SOC_STM32H7A3XX
 	bool
 	select SOC_SERIES_STM32H7X
@@ -101,3 +109,4 @@ config SOC
 	default "stm32h747xx" if SOC_STM32H747XX_M7 || SOC_STM32H747XX_M4
 	default "stm32h750xx" if SOC_STM32H750XX
 	default "stm32h753xx" if SOC_STM32H753XX
+	default "stm32h755xx" if SOC_STM32H755XX_M7 || SOC_STM32H755XX_M4