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dts: rt10xx: Fix SAI dts entries

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The clock gate register bits were incorrectly defined

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit is contained in:
Mahesh Mahadevan 2022-09-16 10:17:08 -05:00
parent 46eaa81ac0
commit 5bebbb91b9
1 changed files with 3 additions and 3 deletions
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6
dts/arm/nxp/nxp_rt10xx.dtsi
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@ -875,7 +875,7 @@
#size-cells = <0>;
#pinmux-cells = <2>;
reg = <0x40384000 0x4000>;
clocks = <&ccm IMX_CCM_SAI1_CLK 0x7C 2>;
clocks = <&ccm IMX_CCM_SAI1_CLK 0x7C 18>;
/* Audio PLL Output Frequency is determined by:
* (Fref * (DIV_SELECT + NUM/DENOM)) / POST_DIV
* = (24MHz * (32 + 77 / 100)) / 1 = 786.48 MHz
@ -913,7 +913,7 @@
#size-cells = <0>;
#pinmux-cells = <2>;
reg = <0x40388000 0x4000>;
clocks = <&ccm IMX_CCM_SAI2_CLK 0x7C 2>;
clocks = <&ccm IMX_CCM_SAI2_CLK 0x7C 20>;
pre-div = <0>;
podf = <63>;
pll-clocks = <&anatop 0x70 0xC000 0x0>,
@ -938,7 +938,7 @@
#size-cells = <0>;
#pinmux-cells = <2>;
reg = <0x4038C000 0x4000>;
clocks = <&ccm IMX_CCM_SAI3_CLK 0x7C 2>;
clocks = <&ccm IMX_CCM_SAI3_CLK 0x7C 22>;
pre-div = <0>;
podf = <63>;
pll-clocks = <&anatop 0x70 0xC000 0>,