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drivers: cache: andes: Dynamically calculate L2 cache parameters

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Enhance the driver to calculate the L2 cache line size and number
of ways at runtime. The L2 cache line size is assumed to match
the L1 cache line size, while the number of ways is determined
based on the total L2 cache size.

Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
This commit is contained in:
Wei-Tai Lee 2024-11-11 17:35:04 +08:00 committed by Benjamin Cabé
parent 92aeb787c7
commit 5cf6137b38
3 changed files with 18 additions and 17 deletions
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4
drivers/cache/Kconfig.andes vendored
View file

@ -2,8 +2,6 @@
#
# Copyright (c) 2024 ANDES Technology Inc.
DT_COMPAT_ANDESTECH_L2C := andestech,l2c
config CACHE_ANDES
bool "ANDES external cache driver"
default y
@ -18,7 +16,7 @@ if CACHE_ANDES
config L2C_INCLUSIVE_POLICY
bool
depends on $(dt_compat_enabled,$(DT_COMPAT_ANDESTECH_L2C))
depends on DT_HAS_ANDESTECH_L2C_ENABLED
help
When L2 cache is inclusive of L1, CPU only needs to perform operations
on L2 cache, instead of on both L1 and L2 caches.

2
drivers/cache/cache_andes.c vendored
View file

@ -544,7 +544,7 @@ static int andes_cache_init(void)
}
}
cache_cfg.l2_cache_size = nds_l2_cache_init();
cache_cfg.l2_cache_size = nds_l2_cache_init(cache_cfg.data_line_size);
cache_cfg.l2_cache_inclusive = nds_l2_cache_is_inclusive();
return 0;

29
drivers/cache/cache_andes_l2.h vendored
View file

@ -54,6 +54,7 @@ struct nds_l2_cache_config {
uint32_t status_offset;
uint16_t status_shift;
uint8_t version;
uint8_t line_size;
};
static struct nds_l2_cache_config l2_cache_cfg;
@ -78,14 +79,16 @@ static ALWAYS_INLINE void nds_l2_cache_wait_status(uint8_t hart_id)
static ALWAYS_INLINE int nds_l2_cache_all(int op)
{
/* L2 cache fixed to 64 byte cache line size and 16 way */
const unsigned long line_size = 64, ways = 16;
unsigned long sets, index, cmd;
unsigned long ways, sets, index, cmd;
uint8_t hart_id;
unsigned long status = csr_read(mstatus);
if (!l2_cache_cfg.size) {
return -ENOTSUP;
} else if (l2_cache_cfg.size >= 128 * 1024) {
ways = 16;
} else {
ways = 8;
}
if (csr_read(NDS_MMSC_CFG) & MMSC_CFG_VCCTL_2) {
@ -118,14 +121,14 @@ static ALWAYS_INLINE int nds_l2_cache_all(int op)
/* Wait L2 CCTL Commands finished */
nds_l2_cache_wait_status(hart_id);
} else {
sets = l2_cache_cfg.size / (ways * line_size);
sets = l2_cache_cfg.size / (ways * l2_cache_cfg.line_size);
/* Invalidate all cache line by each way and each set */
for (int j = 0; j < ways; j++) {
/* Index of way */
index = j << L2C_CCTLACC_WAY_SHIFT;
for (int i = 0; i < sets; i++) {
/* Index of set */
index += line_size;
index += l2_cache_cfg.line_size;
/* Invalidate each cache line */
sys_write32(index, L2C_CCTLACC(hart_id));
@ -142,7 +145,6 @@ static ALWAYS_INLINE int nds_l2_cache_all(int op)
static ALWAYS_INLINE int nds_l2_cache_range(void *addr, size_t size, int op)
{
const unsigned long line_size = 64;
unsigned long last_byte, align_addr, cmd;
uint8_t hart_id;
@ -165,13 +167,13 @@ static ALWAYS_INLINE int nds_l2_cache_range(void *addr, size_t size, int op)
}
last_byte = (unsigned long)addr + size - 1;
align_addr = ROUND_DOWN(addr, line_size);
align_addr = ROUND_DOWN(addr, l2_cache_cfg.line_size);
hart_id = arch_proc_id();
while (align_addr <= last_byte) {
sys_write32(align_addr, L2C_CCTLACC(hart_id));
sys_write32(cmd, L2C_CCTLCMD(hart_id));
align_addr += line_size;
align_addr += l2_cache_cfg.line_size;
/* Wait L2 CCTL Commands finished */
nds_l2_cache_wait_status(hart_id);
@ -204,9 +206,10 @@ static ALWAYS_INLINE void nds_l2_cache_disable(void)
}
}
static ALWAYS_INLINE int nds_l2_cache_init(void)
static ALWAYS_INLINE int nds_l2_cache_init(uint8_t line_size)
{
unsigned long line_size;
unsigned long size;
uint32_t l2c_ctrl;
#if defined(CONFIG_SYSCON)
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(syscon), andestech_atcsmu100, okay)
@ -230,10 +233,10 @@ static ALWAYS_INLINE int nds_l2_cache_init(void)
#endif /* andestech_atcsmu100 dts node status okay */
#endif /* defined(CONFIG_SYSCON) */
uint32_t l2c_ctrl;
l2_cache_cfg.line_size = line_size;
line_size = (sys_read32(L2C_CONFIG) >> L2C_CONFIG_SIZE_SHIFT) & BIT_MASK(7);
l2_cache_cfg.size = line_size * 128 * 1024;
size = (sys_read32(L2C_CONFIG) >> L2C_CONFIG_SIZE_SHIFT) & BIT_MASK(7);
l2_cache_cfg.size = size * 128 * 1024;
if (sys_read32(L2C_CONFIG) & L2C_CONFIG_MAP) {
l2_cache_cfg.cmd_offset = 0x10;