From 5f53afca0a42ed561ea08eb4334b63016f0059d2 Mon Sep 17 00:00:00 2001 From: Declan Snyder Date: Thu, 7 Mar 2024 16:26:09 -0600 Subject: [PATCH] soc: nxp: Add RW SOC Family Add SOC definition for NXP RW Family Signed-off-by: Declan Snyder --- MAINTAINERS.yml | 1 + .../clock_control/clock_control_mcux_syscon.c | 3 + modules/Kconfig.mcux | 2 +- soc/nxp/rw/CMakeLists.txt | 13 + soc/nxp/rw/Kconfig | 87 +++ soc/nxp/rw/Kconfig.defconfig | 68 +++ soc/nxp/rw/Kconfig.soc | 60 ++ soc/nxp/rw/boot_header.ld | 10 + soc/nxp/rw/flexspi_clock_setup.c | 24 + soc/nxp/rw/flexspi_clock_setup.h | 13 + soc/nxp/rw/pinctrl_defs.h | 555 ++++++++++++++++++ soc/nxp/rw/pinctrl_soc.h | 46 ++ soc/nxp/rw/soc.c | 189 ++++++ soc/nxp/rw/soc.h | 24 + soc/nxp/rw/soc.yml | 7 + west.yml | 2 +- 16 files changed, 1102 insertions(+), 2 deletions(-) create mode 100644 soc/nxp/rw/CMakeLists.txt create mode 100644 soc/nxp/rw/Kconfig create mode 100644 soc/nxp/rw/Kconfig.defconfig create mode 100644 soc/nxp/rw/Kconfig.soc create mode 100644 soc/nxp/rw/boot_header.ld create mode 100644 soc/nxp/rw/flexspi_clock_setup.c create mode 100644 soc/nxp/rw/flexspi_clock_setup.h create mode 100644 soc/nxp/rw/pinctrl_defs.h create mode 100644 soc/nxp/rw/pinctrl_soc.h create mode 100644 soc/nxp/rw/soc.c create mode 100644 soc/nxp/rw/soc.h create mode 100644 soc/nxp/rw/soc.yml diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 80b68128e2b..2b44108f2a3 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3332,6 +3332,7 @@ NXP Platforms (MCU): - soc/nxp/imxrt/ - soc/nxp/kinetis/ - soc/nxp/lpc/ + - soc/nxp/rw/ - dts/arm/nxp/ - samples/boards/nxp*/ files-regex-exclude: diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index 5386b41ed04..61eb0481abf 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -158,9 +158,12 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate( #if defined(CONFIG_PWM_MCUX_SCTIMER) case MCUX_SCTIMER_CLK: #endif + +#ifndef CONFIG_SOC_SERIES_RW6XX case MCUX_BUS_CLK: *rate = CLOCK_GetFreq(kCLOCK_BusClk); break; +#endif #if defined(CONFIG_I3C_MCUX) case MCUX_I3C_CLK: diff --git a/modules/Kconfig.mcux b/modules/Kconfig.mcux index 21658c1ebd0..c1760ffd649 100644 --- a/modules/Kconfig.mcux +++ b/modules/Kconfig.mcux @@ -6,7 +6,7 @@ config HAS_MCUX bool depends on SOC_FAMILY_KINETIS || SOC_FAMILY_NXP_IMX || SOC_FAMILY_LPC || \ - SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT + SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT || SOC_FAMILY_NXP_RW if HAS_MCUX config MCUX_CORE_SUFFIX diff --git a/soc/nxp/rw/CMakeLists.txt b/soc/nxp/rw/CMakeLists.txt new file mode 100644 index 00000000000..d4c7cd7af4d --- /dev/null +++ b/soc/nxp/rw/CMakeLists.txt @@ -0,0 +1,13 @@ +# Copyright 2022-2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + flexspi_clock_setup.c + ) + +zephyr_linker_sources_ifdef(CONFIG_NXP_RW6XX_BOOT_HEADER + ROM_START SORT_KEY 0 boot_header.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/rw/Kconfig b/soc/nxp/rw/Kconfig new file mode 100644 index 00000000000..563b9671dba --- /dev/null +++ b/soc/nxp/rw/Kconfig @@ -0,0 +1,87 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RW6XX + select ARM + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_DWT + select CLOCK_CONTROL + select PLATFORM_SPECIFIC_INIT + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select HAS_MCUX_OS_TIMER + select ARM_TRUSTZONE_M + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_MCUX + select HAS_MCUX_FLEXCOMM + select INIT_SYS_PLL + select HAS_MCUX_CACHE + +if SOC_SERIES_RW6XX + +config INIT_SYS_PLL + bool "Initialize SYS PLL" + +menuconfig NXP_RW6XX_BOOT_HEADER + bool "Create boot header" + default y + help + Create data structures required by the boot ROM to boot the + application from an external flash device. + +if NXP_RW6XX_BOOT_HEADER + +choice BOOT_DEVICE + prompt "Boot device selection" + default BOOT_FLEXSPI_NOR + +config BOOT_FLEXSPI_NOR + bool "FlexSPI serial NOR" + +endchoice + +config FLASH_CONFIG_OFFSET + hex "Flash config data offset" + default 0x400 + help + The flash config offset provides the boot ROM with the on-board + flash type and parameters. The boot ROM requires a fixed flash conifg + offset for FlexSPI device. + +config IMAGE_VECTOR_TABLE_OFFSET + hex "Image vector table offset" + default 0x1000 + help + The Image Vector Table (IVT) provides the boot ROM with pointers to + the application entry point and device configuration data. The boot + ROM requires a fixed IVT offset for each type of boot device. + +# Used for default value in FLASH_MCUX_FLEXSPI_XIP +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_FLEXSPI := nxp,imx-flexspi +# Macros to shorten Kconfig definitions +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +config FLASH_MCUX_FLEXSPI_XIP + bool "MCUX FlexSPI flash access with xip" + default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) + select XIP + help + Allows for the soc to safely initialize the clocks for the + FlexSpi when planning to execute code in FlexSpi Memory. + +config NXP_RW_ROM_RAMLOADER + depends on !FLASH_MCUX_FLEXSPI_XIP + # Required so that debugger will load image to correct offset + select BUILD_OUTPUT_HEX + bool "Create output image that RW ROM can load from FlexSPI to ram" + help + Builds an output image that the RW BootROM can load from the + FlexSPI boot device into RAM region. The image will be loaded + from FLEXSPI into the region specified by `zephyr,flash` node. + +endif # NXP_RW6XX_BOOT_HEADER + +endif # SOC_SERIES_RW6XX diff --git a/soc/nxp/rw/Kconfig.defconfig b/soc/nxp/rw/Kconfig.defconfig new file mode 100644 index 00000000000..e17dffe663d --- /dev/null +++ b/soc/nxp/rw/Kconfig.defconfig @@ -0,0 +1,68 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RW6XX + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + default 0x1300 if NXP_RW6XX_BOOT_HEADER + +config NUM_IRQS + default 129 +if CORTEX_M_SYSTICK + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 260000000 + +endif # CORTEX_M_SYSTICK + +# The base address is determined from the zephyr,flash node with the following +# precedence: +# FlexSPI base address (if flash node is on a FlexSPI bus) +# node reg property (used for memory regions such as SRAM) + +# Workaround for not being able to have commas in macro arguments + +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_FLEXSPI := nxp,imx-flexspi + +# Macros to shorten Kconfig definitions +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ + if $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +# The RW6xx has no internal flash. If the flash node has a size property, +# use that over the reg property. This is used for the external flash +# present on the board. Otherwise, fallback to the reg property +config FLASH_SIZE + default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ + if $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +if NXP_RW_ROM_RAMLOADER + +FLASH_BASE := $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) +FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1) +config BUILD_OUTPUT_ADJUST_LMA + default "$(FLEXSPI_BASE) - $(FLASH_BASE)" + +endif # NXP_RW_ROM_RAMLOADER + +if FLASH_MCUX_FLEXSPI_XIP + +# Avoid RWW hazards by defaulting logging to disabled +choice FLASH_LOG_LEVEL_CHOICE + default FLASH_LOG_LEVEL_OFF +endchoice + +choice MEMC_LOG_LEVEL_CHOICE + default MEMC_LOG_LEVEL_OFF +endchoice + +endif # FLASH_MCUX_FLEXSPI_XIP + +endif # SOC_SERIES_RW6XX diff --git a/soc/nxp/rw/Kconfig.soc b/soc/nxp/rw/Kconfig.soc new file mode 100644 index 00000000000..115b7721f9a --- /dev/null +++ b/soc/nxp/rw/Kconfig.soc @@ -0,0 +1,60 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_RW + bool + +config SOC_FAMILY + default "nxp_rw" if SOC_FAMILY_NXP_RW + +config SOC_SERIES_RW6XX + bool + select SOC_FAMILY_NXP_RW + +config SOC_SERIES + default "rw6xx" if SOC_SERIES_RW6XX + +config SOC_RW610 + bool + select SOC_SERIES_RW6XX + +config SOC_RW612 + bool + select SOC_SERIES_RW6XX + +config SOC + default "rw610" if SOC_RW610 + default "rw612" if SOC_RW612 + +config SOC_PART_NUMBER_RW612ETA1I + bool + select SOC_RW612 + +config SOC_PART_NUMBER_RW612HNA1I + bool + select SOC_RW612 + +config SOC_PART_NUMBER_RW612UKA1I + bool + select SOC_RW612 + +config SOC_PART_NUMBER_RW610ETA1I + bool + select SOC_RW610 + +config SOC_PART_NUMBER_RW610HNA1I + bool + select SOC_RW610 + +config SOC_PART_NUMBER_RW610UKA1I + bool + select SOC_RW610 + +config SOC_PART_NUMBER + string + default "RW612ETA1I" if SOC_PART_NUMBER_RW612ETA1I + default "RW612HNA1I" if SOC_PART_NUMBER_RW612HNA1I + default "RW612UKA1I" if SOC_PART_NUMBER_RW612UKA1I + default "RW610ETA1I" if SOC_PART_NUMBER_RW610ETA1I + default "RW610HNA1I" if SOC_PART_NUMBER_RW610HNA1I + default "RW610UKA1I" if SOC_PART_NUMBER_RW610UKA1I diff --git a/soc/nxp/rw/boot_header.ld b/soc/nxp/rw/boot_header.ld new file mode 100644 index 00000000000..ee0be5b4753 --- /dev/null +++ b/soc/nxp/rw/boot_header.ld @@ -0,0 +1,10 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +. = CONFIG_FLASH_CONFIG_OFFSET; +KEEP(*(.flash_conf)) +. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; +KEEP(*(.boot_hdr.ivt)) diff --git a/soc/nxp/rw/flexspi_clock_setup.c b/soc/nxp/rw/flexspi_clock_setup.c new file mode 100644 index 00000000000..18c74954bd3 --- /dev/null +++ b/soc/nxp/rw/flexspi_clock_setup.c @@ -0,0 +1,24 @@ +/* + * Copyright 2022-2023 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "flexspi_clock_setup.h" +#ifdef CONFIG_MEMC +#include +#include +#endif + +/** + * @brief Set flexspi clock + */ +void __ramfunc set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider) +{ + CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src); + CLKCTL0->FLEXSPIFCLKDIV |= + CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */ + CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1); + while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK) { + } +} diff --git a/soc/nxp/rw/flexspi_clock_setup.h b/soc/nxp/rw/flexspi_clock_setup.h new file mode 100644 index 00000000000..0f4f58d4aae --- /dev/null +++ b/soc/nxp/rw/flexspi_clock_setup.h @@ -0,0 +1,13 @@ +/* + * Copyright 2022-2023 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _FLEXSPI_CLOCK_SETUP_H_ +#define _FLEXSPI_CLOCK_SETUP_H_ + +#include "fsl_common.h" + +void set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider); + +#endif /* _FLEXSPI_CLOCK_SETUP_H_ */ diff --git a/soc/nxp/rw/pinctrl_defs.h b/soc/nxp/rw/pinctrl_defs.h new file mode 100644 index 00000000000..fac97912722 --- /dev/null +++ b/soc/nxp/rw/pinctrl_defs.h @@ -0,0 +1,555 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_DEFS_H_ +#define ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_DEFS_H_ + +/* Internal macros to pack and extract pin configuration data. */ +/* GPIO configuration packing macros */ +#define IOMUX_OFFSET_ENABLE(offset, enable, shift) \ + ((((offset) << 1) | (enable & 0x1)) << shift) +#define IOMUX_SCTIMER_OUT_CLR(offset, enable) \ + IOMUX_OFFSET_ENABLE(offset, enable, 0) +#define IOMUX_SCTIMER_IN_CLR(offset, enable) \ + IOMUX_OFFSET_ENABLE(offset, enable, 4) +#define IOMUX_CTIMER_CLR(offset, enable)\ + IOMUX_OFFSET_ENABLE(offset, enable, 8) +#define IOMUX_FSEL_CLR(mask) ((mask) << 13) +#define IOMUX_FLEXCOMM_CLR(idx, mask) \ + (((mask) << 45) | ((idx) << 56)) + +/* GPIO configuration extraction macros */ +#define IOMUX_GET_SCTIMER_OUT_CLR_ENABLE(mux) ((mux) & 0x1) +#define IOMUX_GET_SCTIMER_OUT_CLR_OFFSET(mux) (((mux) >> 1) & 0x7) +#define IOMUX_GET_SCTIMER_IN_CLR_ENABLE(mux) (((mux) >> 4) & 0x1) +#define IOMUX_GET_SCTIMER_IN_CLR_OFFSET(mux) (((mux) >> 5) & 0x7) +#define IOMUX_GET_CTIMER_CLR_ENABLE(mux) (((mux) >> 8) & 0x1ULL) +#define IOMUX_GET_CTIMER_CLR_OFFSET(mux) (((mux) >> 9) & 0xFULL) +#define IOMUX_GET_FSEL_CLR_MASK(mux) (((mux) >> 13) & 0xFFFFFFFFULL) +#define IOMUX_GET_FLEXCOMM_CLR_MASK(mux) \ + (((mux) >> 45) & 0x7FFULL) +#define IOMUX_GET_FLEXCOMM_CLR_IDX(mux) \ + (((mux) >> 56) & 0xF) + +/* Pin mux type and gpio offset macros */ +#define IOMUX_GPIO_IDX(x) ((x) & 0x7F) +#define IOMUX_TYPE(x) (((x) & 0xF) << 7) +#define IOMUX_GET_GPIO_IDX(mux) ((mux) & 0x7F) +#define IOMUX_GET_TYPE(mux) (((mux) >> 7) & 0xF) + +/* Flexcomm specific macros */ +#define IOMUX_FLEXCOMM_IDX(x) (((x) & 0xF) << 11) +#define IOMUX_FLEXCOMM_BIT(x) (((x) & 0xF) << 15) +#define IOMUX_GET_FLEXCOMM_IDX(mux) (((mux) >> 11) & 0xF) +#define IOMUX_GET_FLEXCOMM_BIT(mux) (((mux) >> 15) & 0xF) + +/* Function select specific macros */ +#define IOMUX_FSEL_BIT(mux) (((mux) & 0x1F) << 11) +#define IOMUX_GET_FSEL_BIT(mux) (((mux) >> 11) & 0x1F) + +/* CTimer specific macros */ +#define IOMUX_CTIMER_BIT(x) (((x) & 0xF) << 11) +#define IOMUX_GET_CTIMER_BIT(mux) (((mux) >> 11) & 0xF) + +/* SCtimer specific macros */ +#define IOMUX_SCTIMER_BIT(x) (((x) & 0xF) << 11) +#define IOMUX_GET_SCTIMER_BIT(mux) (((mux) >> 11) & 0xF) + + +/* Mux Types */ +#define IOMUX_FLEXCOMM 0x0 +#define IOMUX_FSEL 0x1 +#define IOMUX_CTIMER_IN 0x2 +#define IOMUX_CTIMER_OUT 0x3 +#define IOMUX_SCTIMER_IN 0x4 +#define IOMUX_SCTIMER_OUT 0x5 +#define IOMUX_GPIO 0x6 +#define IOMUX_SGPIO 0x7 +#define IOMUX_AON 0x8 + + +/* Pin configuration settings */ +#define IOMUX_PAD_PULL(x) (((x) & 0x3) << 19) +#define IOMUX_PAD_SLEW(x) (((x) & 0x3) << 21) +#define IOMUX_PAD_SLEEP_FORCE(en, val) \ + ((((en) & 0x1) << 24) | (((val) & 0x1) << 23)) +#define IOMUX_PAD_GET_PULL(mux) (((mux) >> 19) & 0x3) +#define IOMUX_PAD_GET_SLEW(mux) (((mux) >> 21) & 0x3) +#define IOMUX_PAD_GET_SLEEP_FORCE_EN(mux) (((mux) >> 24) & 0x1) +#define IOMUX_PAD_GET_SLEEP_FORCE_VAL(mux) (((mux) >> 23) & 0x1) + +/* + * GPIO mux options. These options are used to clear all alternate + * pin functions, so the pin controller will use GPIO mode. + */ + +#define IOMUX_GPIO_CLR_0 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_1 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(1ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_2 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x32eULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_3 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x22eULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_4 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x2dULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x800000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(1ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(1ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_5 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_6 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_7 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0xedULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_8 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_9 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_10 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_11 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x40ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(8ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(8ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_12 \ + (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x80ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8020ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(2ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_13 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(3ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_14 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(4ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_15 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0xedULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_16 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_17 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_18 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x80ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0xc600ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_19 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_20 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_21 \ + (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x40ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(5ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_22 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x40ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_23 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x80ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_24 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x40000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(6ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_25 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0xedULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x10000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(7ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_26 \ + (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x80000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(4ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(4ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_27 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x10000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(5ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(5ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_28 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_29 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_30 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_31 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_32 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_33 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_34 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_35 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(6ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(6ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_36 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(7ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(7ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_37 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(8ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_38 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(9ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_39 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(10ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_40 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_41 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_42 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_43 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_44 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_45 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_46 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_47 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_48 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_49 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_50 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x22000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_51 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x40ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x40810ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(11ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_52 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x80ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x80810ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(12ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_53 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x100810ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(13ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_54 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0xedULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x200810ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(14ULL, 1ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_55 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x400000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(9ULL, 1ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(9ULL, 1ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_56 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8000800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_57 \ + (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x8000800ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_58 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_59 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_60 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_61 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x20000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_62 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_CLR_63 \ + (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ + IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \ + IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ + IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ + IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ + +#define IOMUX_GPIO_OPS \ + IOMUX_GPIO_CLR_0, IOMUX_GPIO_CLR_1, IOMUX_GPIO_CLR_2, IOMUX_GPIO_CLR_3, \ + IOMUX_GPIO_CLR_4, IOMUX_GPIO_CLR_5, IOMUX_GPIO_CLR_6, IOMUX_GPIO_CLR_7, \ + IOMUX_GPIO_CLR_8, IOMUX_GPIO_CLR_9, IOMUX_GPIO_CLR_10, IOMUX_GPIO_CLR_11, \ + IOMUX_GPIO_CLR_12, IOMUX_GPIO_CLR_13, IOMUX_GPIO_CLR_14, IOMUX_GPIO_CLR_15, \ + IOMUX_GPIO_CLR_16, IOMUX_GPIO_CLR_17, IOMUX_GPIO_CLR_18, IOMUX_GPIO_CLR_19, \ + IOMUX_GPIO_CLR_20, IOMUX_GPIO_CLR_21, IOMUX_GPIO_CLR_22, IOMUX_GPIO_CLR_23, \ + IOMUX_GPIO_CLR_24, IOMUX_GPIO_CLR_25, IOMUX_GPIO_CLR_26, IOMUX_GPIO_CLR_27, \ + IOMUX_GPIO_CLR_28, IOMUX_GPIO_CLR_29, IOMUX_GPIO_CLR_30, IOMUX_GPIO_CLR_31, \ + IOMUX_GPIO_CLR_32, IOMUX_GPIO_CLR_33, IOMUX_GPIO_CLR_34, IOMUX_GPIO_CLR_35, \ + IOMUX_GPIO_CLR_36, IOMUX_GPIO_CLR_37, IOMUX_GPIO_CLR_38, IOMUX_GPIO_CLR_39, \ + IOMUX_GPIO_CLR_40, IOMUX_GPIO_CLR_41, IOMUX_GPIO_CLR_42, IOMUX_GPIO_CLR_43, \ + IOMUX_GPIO_CLR_44, IOMUX_GPIO_CLR_45, IOMUX_GPIO_CLR_46, IOMUX_GPIO_CLR_47, \ + IOMUX_GPIO_CLR_48, IOMUX_GPIO_CLR_49, IOMUX_GPIO_CLR_50, IOMUX_GPIO_CLR_51, \ + IOMUX_GPIO_CLR_52, IOMUX_GPIO_CLR_53, IOMUX_GPIO_CLR_54, IOMUX_GPIO_CLR_55, \ + IOMUX_GPIO_CLR_56, IOMUX_GPIO_CLR_57, IOMUX_GPIO_CLR_58, IOMUX_GPIO_CLR_59, \ + IOMUX_GPIO_CLR_60, IOMUX_GPIO_CLR_61, IOMUX_GPIO_CLR_62, IOMUX_GPIO_CLR_63 + +#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_DEFS_H_ */ diff --git a/soc/nxp/rw/pinctrl_soc.h b/soc/nxp/rw/pinctrl_soc.h new file mode 100644 index 00000000000..14b40bd69cd --- /dev/null +++ b/soc/nxp/rw/pinctrl_soc.h @@ -0,0 +1,46 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_SOC_H_ + +#include +#include + +#include "pinctrl_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +typedef uint32_t pinctrl_soc_pin_t; + + +#define Z_PINCTRL_IOMUX_PINCFG(node_id) \ + (IF_ENABLED(DT_PROP(node_id, bias_pull_down), \ + (IOMUX_PAD_PULL(0x2) |)) /* pull down */ \ + IF_ENABLED(DT_PROP(node_id, bias_pull_up), \ + (IOMUX_PAD_PULL(0x1) |)) /* pull up */ \ + IF_ENABLED(DT_NODE_HAS_PROP(node_id, sleep_output), /* force output */ \ + IOMUX_PAD_SLEEP_FORCE(0x1, DT_ENUM_IDX(node_id, sleep_output))) \ + IOMUX_PAD_SLEW(DT_ENUM_IDX(node_id, slew_rate))) /* slew rate */ + + +#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \ + DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOMUX_PINCFG(group), + + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ + DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)} + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_SOC_H_ */ diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c new file mode 100644 index 00000000000..4f509ef5425 --- /dev/null +++ b/soc/nxp/rw/soc.c @@ -0,0 +1,189 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include "soc.h" +#include "flexspi_clock_setup.h" +#include "fsl_ocotp.h" +#ifdef CONFIG_NXP_RW6XX_BOOT_HEADER +extern char z_main_stack[]; +extern char _flash_used[]; + +extern void z_arm_reset(void); +extern void z_arm_nmi(void); +extern void z_arm_hard_fault(void); +extern void z_arm_mpu_fault(void); +extern void z_arm_bus_fault(void); +extern void z_arm_usage_fault(void); +extern void z_arm_secure_fault(void); +extern void z_arm_svc(void); +extern void z_arm_debug_monitor(void); +extern void z_arm_pendsv(void); +extern void sys_clock_isr(void); +extern void z_arm_exc_spurious(void); + +__imx_boot_ivt_section void (*const image_vector_table[])(void) = { + (void (*)())(z_main_stack + CONFIG_MAIN_STACK_SIZE), /* 0x00 */ + z_arm_reset, /* 0x04 */ + z_arm_nmi, /* 0x08 */ + z_arm_hard_fault, /* 0x0C */ + z_arm_mpu_fault, /* 0x10 */ + z_arm_bus_fault, /* 0x14 */ + z_arm_usage_fault, /* 0x18 */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + z_arm_secure_fault, /* 0x1C */ +#else + z_arm_exc_spurious, +#endif /* CONFIG_ARM_SECURE_FIRMWARE */ + (void (*)())_flash_used, /* 0x20, imageLength. */ + 0, /* 0x24, imageType (Plain Image) */ + 0, /* 0x28, authBlockOffset/crcChecksum */ + z_arm_svc, /* 0x2C */ + z_arm_debug_monitor, /* 0x30 */ + (void (*)())image_vector_table, /* 0x34, imageLoadAddress. */ + z_arm_pendsv, /* 0x38 */ +#if defined(CONFIG_SYS_CLOCK_EXISTS) && defined(CONFIG_CORTEX_M_SYSTICK_INSTALL_ISR) + sys_clock_isr, /* 0x3C */ +#else + z_arm_exc_spurious, +#endif +}; +#endif /* CONFIG_NXP_RW6XX_BOOT_HEADER */ + +const clock_avpll_config_t avpll_config = { + .ch1Freq = kCLOCK_AvPllChFreq12p288m, + .ch2Freq = kCLOCK_AvPllChFreq64m, + .enableCali = true +}; + +/** + * @brief Initialize the system clocks and peripheral clocks + * + * This function is called from the power management code as the + * clock needs to be re-initialized on exit from Standby mode. Hence + * this function is relocated to RAM. + */ +__ramfunc void clock_init(void) +{ + POWER_DisableGDetVSensors(); + + if ((PMU->CAU_SLP_CTRL & PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK) == 0U) { + /* LPOSC not enabled, enable it */ + CLOCK_EnableClock(kCLOCK_RefClkCauSlp); + } + if ((SYSCTL2->SOURCE_CLK_GATE & SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK) != 0U) { + /* REFCLK_SYS not enabled, enable it */ + CLOCK_EnableClock(kCLOCK_RefClkSys); + } + + /* Initialize T3 clocks and t3pll_mci_48_60m_irc configured to 48.3MHz */ + CLOCK_InitT3RefClk(kCLOCK_T3MciIrc48m); + /* Enable FFRO */ + CLOCK_EnableClock(kCLOCK_T3PllMciIrcClk); + /* Enable T3 256M clock and SFRO */ + CLOCK_EnableClock(kCLOCK_T3PllMci256mClk); + + /* Move FLEXSPI clock source to T3 256m / 4 to avoid instruction/data fetch issue in XIP + * when updating PLL and main clock. + */ + set_flexspi_clock(FLEXSPI, 6U, 4U); + + /* First let M33 run on SOSC */ + CLOCK_AttachClk(kSYSOSC_to_MAIN_CLK); + CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1); + + /* tcpu_mci_clk configured to 260MHz, tcpu_mci_flexspi_clk 312MHz. */ + CLOCK_InitTcpuRefClk(3120000000UL, kCLOCK_TcpuFlexspiDiv10); + /* Enable tcpu_mci_clk 260MHz. Keep tcpu_mci_flexspi_clk gated. */ + CLOCK_EnableClock(kCLOCK_TcpuMciClk); + + /* tddr_mci_flexspi_clk 320MHz */ + CLOCK_InitTddrRefClk(kCLOCK_TddrFlexspiDiv10); + CLOCK_EnableClock(kCLOCK_TddrMciFlexspiClk); /* 320MHz */ + + /* Enable AUX0 PLL to 260 MHz */ + CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U); + + /* Init AVPLL and enable both channels */ + CLOCK_InitAvPll(&avpll_config); + CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U); + + /* Configure MainPll to 260MHz, then let CM33 run on Main PLL. */ + CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1U); + CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U); + CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); + + /* Set SYSTICKFCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U); + CLOCK_AttachClk(kSYSTICK_DIV_to_SYSTICK_CLK); + + /* Set PLL FRG clock to 20MHz. */ + CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U); + + /* Call function set_flexspi_clock() to set flexspi clock source to aux0_pll_clk in XIP. */ + set_flexspi_clock(FLEXSPI, 2U, 2U); + +/* Any flexcomm can be USART */ +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay)) && CONFIG_SERIAL + CLOCK_SetFRGClock(&(const clock_frg_clk_config_t){0, kCLOCK_FrgPllDiv, 255, 0}); + CLOCK_AttachClk(kFRG_to_FLEXCOMM0); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_usart, okay)) && CONFIG_SERIAL + CLOCK_SetFRGClock(&(const clock_frg_clk_config_t){1, kCLOCK_FrgPllDiv, 255, 0}); + CLOCK_AttachClk(kFRG_to_FLEXCOMM1); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_usart, okay)) && CONFIG_SERIAL + CLOCK_SetFRGClock(&(const clock_frg_clk_config_t){2, kCLOCK_FrgPllDiv, 255, 0}); + CLOCK_AttachClk(kFRG_to_FLEXCOMM2); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_usart, okay)) && CONFIG_SERIAL + CLOCK_SetFRGClock(&(const clock_frg_clk_config_t){3, kCLOCK_FrgPllDiv, 255, 0}); + CLOCK_AttachClk(kFRG_to_FLEXCOMM3); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm14), nxp_lpc_usart, okay)) && CONFIG_SERIAL + CLOCK_SetFRGClock(&(const clock_frg_clk_config_t){14, kCLOCK_FrgPllDiv, 255, 0}); + CLOCK_AttachClk(kFRG_to_FLEXCOMM14); +#endif + +} + +/** + * + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the timer device driver, if required. + * + * @return 0 + */ + +static int nxp_rw600_init(void) +{ + + /* Initialize clock */ + clock_init(); + + return 0; +} + +void z_arm_platform_init(void) +{ + /* This is provided by the SDK */ + SystemInit(); +} + +SYS_INIT(nxp_rw600_init, PRE_KERNEL_1, 0); diff --git a/soc/nxp/rw/soc.h b/soc/nxp/rw/soc.h new file mode 100644 index 00000000000..66a2cf836b5 --- /dev/null +++ b/soc/nxp/rw/soc.h @@ -0,0 +1,24 @@ +/* + * Copyright 2022-2023 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#ifndef _ASMLANGUAGE +#include +#include + +/* Add include for DTS generated information */ +#include + +#endif /* !_ASMLANGUAGE */ + + +#ifdef CONFIG_MEMC +uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate); +#endif + + +#endif /* _SOC__H_ */ diff --git a/soc/nxp/rw/soc.yml b/soc/nxp/rw/soc.yml new file mode 100644 index 00000000000..324b27ef219 --- /dev/null +++ b/soc/nxp/rw/soc.yml @@ -0,0 +1,7 @@ +family: +- name: nxp_rw + series: + - name: rw61x + socs: + - name: rw612 + - name: rw610 diff --git a/west.yml b/west.yml index 9d3acf9af5b..1eb17cbc69d 100644 --- a/west.yml +++ b/west.yml @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: ac24626660f96dc734714896878dd6e1157c1c29 + revision: 259bc153dd5b9dbc5cbe63d2d644a61ee83b7496 path: modules/hal/nxp groups: - hal