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boards: litex_vexriscv: dts: Reorder liteeth registers

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This is just a cosmetic change to avoid a warning:
"unit-address and first reg (0xb0000000)
don't match for ethernet@e0009800"

Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This commit is contained in:
Mateusz Holenko 2019-10-21 10:55:17 +02:00 committed by Jukka Rissanen
parent 008241311b
commit 65e4178071
1 changed files with 2 additions and 2 deletions
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dts/riscv/riscv32-litex-vexriscv.dtsi
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@ -68,9 +68,9 @@
compatible = "litex,eth0";
interrupt-parent = <&intc0>;
interrupts = <3 0>;
reg = <0xb0000000 0x2000 0xe0009800 0x6b>;
reg = <0xe0009800 0x6b 0xb0000000 0x2000>;
local-mac-address = [10 e2 d5 00 00 02];
reg-names = "buffers", "control";
reg-names = "control", "buffers";
label = "eth0";
status = "disabled";
};