drivers: mbox: rework andes mbox plic to leverage intc_plic driver
Andes MBOX PLIC-SW use the same hardware as intc_plic driver. Reworked mbox_andes_plic_sw implementation to leverage the intc_plic driver. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng
Carles Cufí
parent
6caf803a41
commit
6658b9c02c
2 changed files with 91 additions and 153 deletions
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@ -8,7 +8,8 @@
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config MBOX_ANDES_PLIC_SW
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bool "MBOX Andes PLIC-SW driver"
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default y
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depends on DT_HAS_ANDESTECH_PLIC_SW_ENABLED
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depends on DT_HAS_ANDESTECH_MBOX_PLIC_SW_ENABLED
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depends on PLIC_SUPPORTS_SOFT_INTERRUPT
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select DYNAMIC_INTERRUPTS
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help
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Enable driver for the Andes IPM mailbox controller.
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Says n if not sure.
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Enable the driver for the Andes PLIC-SW based MBOX controller.
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@ -8,215 +8,152 @@
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#define LOG_LEVEL CONFIG_MBOX_LOG_LEVEL
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/drivers/interrupt_controller/riscv_plic.h>
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LOG_MODULE_REGISTER(mbox_andes_plic_sw);
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#define DT_DRV_COMPAT andestech_plic_sw
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#define DT_DRV_COMPAT andestech_mbox_plic_sw
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#define IRQ_REG(n) (n >> 5)
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#define PLIC_BASE(dev) \
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((const struct mbox_andes_conf * const)(dev)->config)->base
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#define REG_PRIORITY(dev, irq) \
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(PLIC_BASE(dev) + 0x0 + (irq << 2))
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#define REG_PENDING(dev, irq) \
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(PLIC_BASE(dev) + 0x1000 + (IRQ_REG(irq) << 2))
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#define REG_ENABLE(dev, hart, irq) \
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(PLIC_BASE(dev) + 0x2000 + (hart << 7) + IRQ_REG(irq))
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#define REG_CLAIM(dev, hart) \
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(PLIC_BASE(dev) + 0x200004 + (hart << 12))
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#define IPI_NUM DT_INST_PROP(0, channel_max)
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static struct mbox_andes_data {
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mbox_callback_t cb[IPI_NUM];
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void *user_data[IPI_NUM];
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uint32_t enabled_channel[CONFIG_MP_MAX_NUM_CPUS];
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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uint32_t reg_cb_channel;
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uint32_t ipi_channel;
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#endif
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} andes_mbox_data;
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static struct mbox_andes_conf {
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uint32_t base;
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uint32_t channel_max;
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} andes_mbox_conf = {
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.base = DT_INST_REG_ADDR(0),
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.channel_max = IPI_NUM,
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struct mbox_plic_data {
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mbox_callback_t *cb;
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void **user_data;
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struct k_spinlock lock;
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};
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static struct k_spinlock mbox_syn;
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static void plic_sw_irq_set_pending(const struct device *dev, uint32_t irq)
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{
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uint32_t pend;
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k_spinlock_key_t key = k_spin_lock(&mbox_syn);
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pend = sys_read32(REG_PENDING(dev, irq));
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pend |= BIT(irq);
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sys_write32(pend, REG_PENDING(dev, irq));
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k_spin_unlock(&mbox_syn, key);
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}
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struct mbox_plic_conf {
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uint32_t channel_max;
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const uint32_t *irq_sources;
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};
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static inline bool is_channel_valid(const struct device *dev, uint32_t ch)
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{
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const struct mbox_andes_conf *conf = dev->config;
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const struct mbox_plic_conf *conf = dev->config;
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return (ch <= conf->channel_max);
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return (ch <= conf->channel_max) && conf->irq_sources[ch];
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}
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static int mbox_andes_send(const struct device *dev, uint32_t ch,
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const struct mbox_msg *msg)
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static int mbox_plic_send(const struct device *dev, uint32_t ch, const struct mbox_msg *msg)
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{
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const struct mbox_plic_conf *conf = dev->config;
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if (msg) {
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LOG_WRN("Sending data not supported");
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LOG_WRN("Transfer mode is not supported");
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}
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if (!is_channel_valid(dev, ch)) {
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return -EINVAL;
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}
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/* Send IPI by triggering the pending register of PLIC SW. */
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plic_sw_irq_set_pending(dev, ch + 1);
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/* Send the MBOX signal by setting the Pending bit register in the PLIC. */
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riscv_plic_irq_set_pending(conf->irq_sources[ch]);
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return 0;
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}
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static int mbox_andes_register_callback(const struct device *dev, uint32_t ch,
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mbox_callback_t cb, void *user_data)
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static int mbox_plic_register_callback(const struct device *dev, uint32_t ch, mbox_callback_t cb,
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void *user_data)
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{
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struct mbox_andes_data *data = dev->data;
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const struct mbox_andes_conf *conf = dev->config;
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int ret = 0;
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struct mbox_plic_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&mbox_syn);
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if (ch > conf->channel_max) {
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ret = -EINVAL;
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goto out;
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if (!is_channel_valid(dev, ch)) {
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return -EINVAL;
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}
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#ifdef CONFIG_SCHED_IPI_SUPPORTED
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if (ch & data->ipi_channel & data->reg_cb_channel) {
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ret = -EALREADY;
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goto out;
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}
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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data->reg_cb_channel |= BIT(ch);
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#endif
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data->cb[ch] = cb;
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data->user_data[ch] = user_data;
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out:
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k_spin_unlock(&mbox_syn, key);
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int mbox_andes_mtu_get(const struct device *dev)
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static int mbox_plic_mtu_get(const struct device *dev)
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{
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/* We only support signalling */
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return 0;
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/* MBOX PLIC only support signalling mode */
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return -ENOTSUP;
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}
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static uint32_t mbox_andes_max_channels_get(const struct device *dev)
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static uint32_t mbox_plic_max_channels_get(const struct device *dev)
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{
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const struct mbox_andes_conf *conf = dev->config;
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const struct mbox_plic_conf *conf = dev->config;
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return conf->channel_max;
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}
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static int mbox_andes_set_enabled(const struct device *dev, uint32_t ch,
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bool enable)
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static int mbox_plic_set_enabled(const struct device *dev, uint32_t ch, bool enable)
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{
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uint32_t en, is_enabled_ch, hartid, cpu_id, irq;
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struct mbox_andes_data *data = dev->data;
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int ret = 0;
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k_spinlock_key_t key = k_spin_lock(&mbox_syn);
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struct mbox_plic_data *data = dev->data;
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const struct mbox_plic_conf *conf = dev->config;
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if (!is_channel_valid(dev, ch)) {
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ret = -EINVAL;
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goto out;
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}
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irq = ch + 1;
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hartid = arch_proc_id();
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cpu_id = _current_cpu->id;
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is_enabled_ch = data->enabled_channel[cpu_id] & BIT(ch);
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if ((!enable && !is_enabled_ch) || (enable && is_enabled_ch)) {
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ret = -EALREADY;
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goto out;
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return -EINVAL;
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}
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if (enable && !(data->cb[ch])) {
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LOG_WRN("Enabling channel without a registered callback\n");
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}
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en = sys_read32(REG_ENABLE(dev, hartid, irq));
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if (enable) {
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data->enabled_channel[cpu_id] |= BIT(ch);
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sys_write32(1, REG_PRIORITY(dev, irq));
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en |= BIT(irq);
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riscv_plic_irq_enable(conf->irq_sources[ch]);
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} else {
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data->enabled_channel[cpu_id] &= ~BIT(ch);
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en &= ~BIT(irq);
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riscv_plic_irq_disable(conf->irq_sources[ch]);
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}
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sys_write32(en, REG_ENABLE(dev, hartid, irq));
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out:
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k_spin_unlock(&mbox_syn, key);
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return ret;
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}
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static void andes_plic_sw_irq_handler(const struct device *dev)
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{
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struct mbox_andes_data *data = dev->data;
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uint32_t irq, ch, hartid;
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hartid = arch_proc_id();
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/* PLIC claim: Get the SW IRQ number generating the interrupt. */
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irq = sys_read32(REG_CLAIM(dev, hartid));
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ch = irq - 1;
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if (irq) {
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sys_write32(irq, REG_CLAIM(dev, hartid));
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if (data->cb[ch]) {
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/* Only one MAILBOX, id is unused and set to 0 */
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data->cb[ch](dev, ch, data->user_data[ch], NULL);
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}
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}
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}
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static int mbox_andes_init(const struct device *dev)
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{
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/* Setup IRQ handler for PLIC SW driver */
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IRQ_CONNECT(RISCV_IRQ_MSOFT, 1,
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andes_plic_sw_irq_handler, DEVICE_DT_INST_GET(0), 0);
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#ifndef CONFIG_SMP
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irq_enable(RISCV_IRQ_MSOFT);
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#endif
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return 0;
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}
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static const struct mbox_driver_api mbox_andes_driver_api = {
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.send = mbox_andes_send,
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.register_callback = mbox_andes_register_callback,
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.mtu_get = mbox_andes_mtu_get,
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.max_channels_get = mbox_andes_max_channels_get,
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.set_enabled = mbox_andes_set_enabled,
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static const struct mbox_driver_api mbox_plic_driver_api = {
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.send = mbox_plic_send,
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.register_callback = mbox_plic_register_callback,
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.mtu_get = mbox_plic_mtu_get,
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.max_channels_get = mbox_plic_max_channels_get,
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.set_enabled = mbox_plic_set_enabled,
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};
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DEVICE_DT_INST_DEFINE(0, mbox_andes_init, NULL, &andes_mbox_data,
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&andes_mbox_conf, PRE_KERNEL_1, CONFIG_MBOX_INIT_PRIORITY,
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&mbox_andes_driver_api);
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#define MBOX_PLIC_ISR_FUNCTION_IDX(node, prop, idx, n) \
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static void mbox_plic_irq_handler##n##_##idx(const struct device *dev) \
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{ \
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struct mbox_plic_data *data = dev->data; \
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const uint32_t irq = DT_IRQ_BY_IDX(node, idx, irq); \
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if (data->cb[irq]) { \
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data->cb[irq](dev, irq, data->user_data[irq], NULL); \
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} \
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}
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#define MBOX_PLIC_ISR_FUNCTION(n) \
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DT_INST_FOREACH_PROP_ELEM_SEP_VARGS(n, interrupt_names, MBOX_PLIC_ISR_FUNCTION_IDX, (), n)
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#define MBOX_PLIC_IRQ_CONNECT_IDX(node, prop, idx, n) \
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IRQ_CONNECT(DT_IRQN_BY_IDX(node, idx), 1, mbox_plic_irq_handler##n##_##idx, \
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DEVICE_DT_INST_GET(n), 0)
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#define MBOX_PLIC_IRQ_CONNECT(n) \
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DT_INST_FOREACH_PROP_ELEM_SEP_VARGS(n, interrupt_names, MBOX_PLIC_IRQ_CONNECT_IDX, (;), n)
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#define MBOX_PLIC_INIT_FUNCTION(n) \
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static int mbox_plic_init##n(const struct device *dev) \
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{ \
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MBOX_PLIC_IRQ_CONNECT(n); \
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return 0; \
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}
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#define MBOX_PLIC_IRQ_SOURCE_IDX(node, prop, idx) \
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[DT_IRQ_BY_IDX(node, idx, irq)] = DT_IRQN_BY_IDX(node, idx)
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#define MBOX_PLIC_IRQ_SOURCE(n) \
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static const unsigned int irq_sources##n[] = {DT_INST_FOREACH_PROP_ELEM_SEP( \
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n, interrupt_names, MBOX_PLIC_IRQ_SOURCE_IDX, (,))};
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#define MBOX_PLIC_DEVICE_INIT(n) \
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MBOX_PLIC_ISR_FUNCTION(n) \
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MBOX_PLIC_INIT_FUNCTION(n) \
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MBOX_PLIC_IRQ_SOURCE(n) \
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static mbox_callback_t mbox_callback##n[ARRAY_SIZE(irq_sources##n)]; \
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static void *user_data##n[ARRAY_SIZE(irq_sources##n)]; \
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static struct mbox_plic_data mbox_plic_data##n = { \
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.cb = mbox_callback##n, \
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.user_data = user_data##n, \
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}; \
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static const struct mbox_plic_conf mbox_plic_conf##n = { \
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.channel_max = ARRAY_SIZE(irq_sources##n), \
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.irq_sources = irq_sources##n, \
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}; \
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DEVICE_DT_INST_DEFINE(n, &mbox_plic_init##n, NULL, &mbox_plic_data##n, &mbox_plic_conf##n, \
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PRE_KERNEL_2, CONFIG_MBOX_INIT_PRIORITY, &mbox_plic_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(MBOX_PLIC_DEVICE_INIT)
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