dts: Add and extend Nordic bindings needed for nRF54H20

Add a set of bindings that will be used in the nRF54H20 SoC definition.
Extend the existing GPIOTE binding with properties needed for this SoC.
Also do a tiny clean-up in the bindings added recently for nRF54L15
(HFXO and LFXO).

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>

dts/bindings/arm/nordic,nrf-uicr-v2.yaml

@@ -0,0 +1,26 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic UICR v2 (User Information Configuration Registers)
+
+compatible: "nordic,nrf-uicr-v2"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  domain:
+    type: int
+    required: true
+    description: |
+      Domain ID of the domain associated with this UICR instance. Must be unique
+      across all UICR instances in the system.
+
+  ptr-ext-uicr:
+    type: phandle
+    required: true
+    description: |
+      Handle of a memory region reserved to contain an Extended UICR instance.
+      The address of that node will be stored in the UICR.PTREXTUICR register.

dts/bindings/clock/nordic,nrf-hfxo.yaml

@@ -5,7 +5,7 @@ description: Nordic nRF high-frequency crystal oscillator
 
 compatible: "nordic,nrf-hfxo"
 
-include: [fixed-clock.yaml]
+include: fixed-clock.yaml
 
 properties:
   clock-frequency:

dts/bindings/clock/nordic,nrf-hsfll.yaml

@@ -0,0 +1,65 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Nordic nRF HSFLL
+
+  The HSFLL mixed-mode IP generates several clock frequencies in the range from
+  64 MHz to 400 MHz (in steps of 16 MHz).
+
+  Usage example:
+
+    hsfll: clock@deadbeef {
+        compatible = "nordic,nrf-hsfll";
+        reg = <0xdeadbeef 0x1000>;
+        clocks = <&fll16m>;
+        clock-frequency = <DT_FREQ_M(320)>;
+        nordic,ficrs = <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>,
+                       <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>,
+                       <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>;
+        nordic,ficr-names = "vsup", "coarse", "fine";
+    };
+
+  Required FICR entries are for VSUP, COARSE and FINE trim values.
+
+compatible: "nordic,nrf-hsfll"
+
+include: [base.yaml, fixed-clock.yaml, nordic-nrf-ficr-client.yaml]
+
+properties:
+  reg:
+    required: true
+
+  clocks:
+    required: true
+
+  clock-frequency:
+    enum:
+      - 64000000
+      - 80000000
+      - 96000000
+      - 112000000
+      - 128000000
+      - 144000000
+      - 160000000
+      - 176000000
+      - 192000000
+      - 208000000
+      - 224000000
+      - 240000000
+      - 256000000
+      - 272000000
+      - 288000000
+      - 304000000
+      - 320000000
+      - 336000000
+      - 352000000
+      - 368000000
+      - 384000000
+      - 400000000
+
+  nordic,ficrs:
+    required: true
+
+  nordic,ficr-names:
+    required: true

dts/bindings/clock/nordic,nrf-lfxo.yaml

@@ -5,7 +5,7 @@ description: Nordic nRF low-frequency crystal oscillator
 
 compatible: "nordic,nrf-lfxo"
 
-include: [fixed-clock.yaml]
+include: fixed-clock.yaml
 
 properties:
   clock-frequency:

dts/bindings/cpu/nordic,vpr.yaml

@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic Semiconductor RISC-V VPR CPU
+
+compatible: "nordic,vpr"
+
+include: riscv,cpus.yaml
+
+properties:
+  nordic,bus-width:
+    type: int
+    enum:
+      - 32
+      - 64
+    required: true
+    description:
+      Bus width of the CPU.

dts/bindings/gpio/nordic,nrf-gpiote.yaml

@@ -5,7 +5,9 @@ description: NRF5 GPIOTE node
 
 compatible: "nordic,nrf-gpiote"
 
-include: base.yaml
+include:
+  - base.yaml
+  - nordic,split-channels.yaml
 
 properties:
   reg:

dts/bindings/interrupt-controller/nordic,nrf-clic.yaml

@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic VPR CLIC
+
+compatible: "nordic,nrf-clic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  "#interrupt-cells":
+    const: 2
+
+interrupt-cells:
+  - irq
+  - priority

dts/bindings/mtd/nordic,mram.yaml

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic MRAM
+
+compatible: nordic,mram
+
+include: soc-nv-flash.yaml
+
+properties:
+  reg:
+    required: true

dts/bindings/mtd/nordic,owned-partitions.yaml

@@ -0,0 +1,89 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Nordic Owned Partitions
+
+  Memory partition table with permission attributes common to its partitions.
+  This is a special case of the Nordic Owned Memory binding.
+
+  Every compatible node is expected to be a child of a memory node, where the
+  listed partitions belong.
+
+  A single memory node can contain multiple partition tables, each with a
+  different set of permissions. For each such table, the smallest memory region
+  spanning the contained partitions will be recorded in the UICR. These regions
+  are allowed to contain gaps between the partitions, but this is discouraged.
+
+  Example:
+
+    mram1x: mram@e000000 {
+        compatible = "nordic,mram";
+        reg = <0xe000000 0x200000>;
+        ...
+
+        rx-partitions {
+            compatible = "nordic,owned-partitions";
+            perm-read;
+            perm-execute;
+            #address-cells = <1>;
+            #size-cells = <1>;
+
+            slot0_partition: partition@c0000 {
+                label = "image-0";
+                reg = <0xc0000 0x40000>;
+            };
+        };
+
+        rw-partitions {
+            compatible = "nordic,owned-partitions";
+            perm-read;
+            perm-write;
+            #address-cells = <1>;
+            #size-cells = <1>;
+
+            slot1_partition: partition@100000 {
+                label = "image-1";
+                reg = <0x100000 0x50000>;
+            };
+            storage_partition: partition@150000 {
+                label = "storage";
+                reg = <0x150000 0x6000>;
+            };
+        };
+    };
+
+  From this example, two memory regions will be inferred:
+
+    - 0x0E0C0000--0x0E100000, with read & execute permissions, containing the
+      partition labeled "image-0".
+    - 0x0E100000--0x0E156000, with read & write permissions, containing the
+      partitions labeled "image-1" and "storage".
+
+compatible: "nordic,owned-partitions"
+
+include:
+  - name: nordic,owned-memory.yaml
+    property-blocklist:
+      - reg
+
+properties:
+  "#address-cells":
+    required: true
+
+  "#size-cells":
+    required: true
+
+child-binding:
+  description: |
+    Partitions in the table are defined as subnodes. Each partition must have a
+    size and an offset relative to the base address of the parent memory node.
+
+  include:
+    - name: base.yaml
+      property-blocklist:
+        - compatible
+
+  properties:
+    reg:
+      required: true

dts/bindings/reserved-memory/nordic,owned-memory.yaml

@@ -0,0 +1,46 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Nordic Owned Memory
+
+  Memory region with permission attributes. Each enabled region of this kind
+  will be recorded in the UICR of the compiled domain. Memory ownership and
+  access is then configured for the domain at boot time, based on the UICR.
+
+compatible: "nordic,owned-memory"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  owner-id:
+    type: int
+    description: |
+      Owner ID of the domain that will own this memory region. If not defined,
+      the ownership will default to the domain being compiled.
+
+      Note: owner ID is not the same as domain ID; see the product specification
+      for details.
+
+  perm-read:
+    type: boolean
+    description: Owner has read access to the region.
+
+  perm-write:
+    type: boolean
+    description: Owner has write access to the region.
+
+  perm-execute:
+    type: boolean
+    description: Owner can execute code from the region.
+
+  perm-secure:
+    type: boolean
+    description: Owner has secure-only access to the region.
+
+  non-secure-callable:
+    type: boolean
+    description: Memory region is used for non-secure-callable code.

dts/bindings/riscv/nordic,nrf-vpr-coprocessor.yaml

@@ -0,0 +1,29 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+compatible: "nordic,nrf-vpr-coprocessor"
+
+description: |
+  VPR coprocessor
+
+  VPR is a RISC-V CPU implementation. VPR instances are exposed to other CPUs as
+  peripherals.
+
+include: base.yaml
+
+properties:
+  cpu:
+    type: int
+    description: |
+      Processor ID of the VPR core.
+
+  execution-memory:
+    type: phandle
+    required: true
+    description: |
+      Memory area from which the VPR core will execute.
+
+  source-memory:
+    type: phandle
+    description: |
+      Memory area or partition from which the VPR code will be loaded.