drivers: watchdog: Refine the atcwdt200 driver's code.
Remove the reset vector setting from driver layer, the reset vector is more suitable to be set at the board layer. Signed-off-by: Kevin Wang <kevinwang821020@google.com>
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1 changed files with 0 additions and 29 deletions
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@ -73,24 +73,10 @@ LOG_MODULE_REGISTER(wdt_andes);
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#define WDT_ST_INTEXPIRED 0x1
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#define WDT_ST_INTEXPIRED_CLR 0x1
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/*
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* SMU(System Management Unit) Registers for hwinfo driver
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*/
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/* Register offset*/
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#define SMU_RESET_WRSR 0x10
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#define SMU_RESET_REGHI 0x60
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#define SMU_RESET_REGLO 0x50
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#define SMU_CMD 0x14
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#define SMU_RESET_CMD 0x3c
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#define WDOGCFG_PERIOD_MIN BIT(7)
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#define WDOGCFG_PERIOD_MAX BIT(14)
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#define EXT_CLOCK_FREQ BIT(15)
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static const struct device *const syscon_dev =
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DEVICE_DT_GET(DT_NODELABEL(syscon));
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static const struct device *const pit_counter_dev =
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DEVICE_DT_GET(DT_NODELABEL(pit0));
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@ -326,24 +312,9 @@ static int wdt_atcwdt200_init(const struct device *dev)
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data->timeout_valid = false;
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data->counter_callback = wdt_counter_cb;
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uint32_t ret;
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counter_start(pit_counter_dev);
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ret = syscon_write_reg(syscon_dev, SMU_RESET_REGLO,
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((uint32_t)((unsigned long)
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K_MEM_PHYS_ADDR(CONFIG_KERNEL_ENTRY))));
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if (ret < 0) {
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return -EINVAL;
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}
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ret = syscon_write_reg(syscon_dev, SMU_RESET_REGHI,
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((uint32_t)((uint64_t)((unsigned long)
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K_MEM_PHYS_ADDR(CONFIG_KERNEL_ENTRY)) >> 32)));
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if (ret < 0) {
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return -EINVAL;
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}
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#ifdef CONFIG_WDT_DISABLE_AT_BOOT
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wdt_atcwdt200_disable(dev);
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#else
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