drivers: interrupt_controller: introduce PINT driver

Introduce PINT driver, for NXP pin interrupt and pattern match engine.
The driver currently supports only the pin interrupt feature of the
PINT.

Add DTS entires for the PINT on LPC and RT devices that support this
peripheral, and remove the interrupt defintions that are PINT specific
from the GPIO module on these devices.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>

drivers/interrupt_controller/CMakeLists.txt

@@ -32,6 +32,7 @@ zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ      intc_vexriscv_litex.
 zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC            intc_nuclei_eclic.c)
 zephyr_library_sources_ifdef(CONFIG_NXP_S32_EIRQ            intc_eirq_nxp_s32.c)
 zephyr_library_sources_ifdef(CONFIG_XMC4XXX_INTC            intc_xmc4xxx.c)
+zephyr_library_sources_ifdef(CONFIG_NXP_PINT                intc_nxp_pint.c)
 
 if(CONFIG_INTEL_VTD_ICTL)
   zephyr_library_include_directories(${ZEPHYR_BASE}/arch/x86/include)

drivers/interrupt_controller/Kconfig

@@ -98,4 +98,6 @@ source "drivers/interrupt_controller/Kconfig.nxp_s32"
 
 source "drivers/interrupt_controller/Kconfig.xmc4xxx"
 
+source "drivers/interrupt_controller/Kconfig.nxp_pint"
+
 endmenu

drivers/interrupt_controller/Kconfig.nxp_pint

@@ -0,0 +1,9 @@
+# Copyright 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config NXP_PINT
+	bool "Pin interrupt and pattern match engine (PINT) for NXP MCUs"
+	default y
+	depends on DT_HAS_NXP_PINT_ENABLED
+	help
+	  Enable PINT driver for NXP MCUs

drivers/interrupt_controller/intc_nxp_pint.c

@@ -0,0 +1,204 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Based on STM32 EXTI driver, which is (c) 2016 Open-RnD Sp. z o.o. */
+
+#include <zephyr/device.h>
+#include <zephyr/irq.h>
+#include <errno.h>
+#include <zephyr/drivers/interrupt_controller/nxp_pint.h>
+
+#include <fsl_inputmux.h>
+
+#define DT_DRV_COMPAT nxp_pint
+
+#define PINT_NODE DT_INST(0, DT_DRV_COMPAT)
+
+static PINT_Type *pint_base = (PINT_Type *)DT_REG_ADDR(PINT_NODE);
+
+/* Describes configuration of PINT IRQ slot */
+struct pint_irq_slot {
+	nxp_pint_cb_t callback;
+	void *user_data;
+	uint8_t pin: 6;
+	uint8_t used: 1;
+};
+
+#define NO_PINT_ID 0xFF
+
+/* Tracks IRQ configuration for each pint interrupt source */
+static struct pint_irq_slot pint_irq_cfg[DT_PROP(PINT_NODE, num_lines)];
+/* Tracks pint interrupt source selected for each pin */
+static uint8_t pin_pint_id[DT_PROP(PINT_NODE, num_inputs)];
+
+#define PIN_TO_INPUT_MUX_CONNECTION(pin) \
+	((PINTSEL_PMUX_ID << PMUX_SHIFT) + (pin))
+
+/* Attaches pin to PINT IRQ slot using INPUTMUX */
+static void attach_pin_to_pint(uint8_t pin, uint8_t pint_slot)
+{
+	INPUTMUX_Init(INPUTMUX);
+
+	/* Three parameters here- INPUTMUX base, the ID of the PINT slot,
+	 * and a integer describing the GPIO pin.
+	 */
+	INPUTMUX_AttachSignal(INPUTMUX, pint_slot,
+			      PIN_TO_INPUT_MUX_CONNECTION(pin));
+
+	/* Disable INPUTMUX after making changes, this gates clock and
+	 * saves power.
+	 */
+	INPUTMUX_Deinit(INPUTMUX);
+}
+
+/**
+ * @brief Enable PINT interrupt source.
+ *
+ * @param pin: pin to use as interrupt source
+ *     0-64, corresponding to GPIO0 pin 1 - GPIO1 pin 31)
+ * @param trigger: one of nxp_pint_trigger flags
+ * @return 0 on success, or negative value on error
+ */
+int nxp_pint_pin_enable(uint8_t pin, enum nxp_pint_trigger trigger)
+{
+	uint8_t slot = 0U;
+
+	if (pin > ARRAY_SIZE(pin_pint_id)) {
+		/* Invalid pin ID */
+		return -EINVAL;
+	}
+	/* Find unused IRQ slot */
+	if (pin_pint_id[pin] != NO_PINT_ID) {
+		slot = pin_pint_id[pin];
+	} else {
+		for (slot = 0; slot < ARRAY_SIZE(pint_irq_cfg); slot++) {
+			if (!pint_irq_cfg[slot].used) {
+				break;
+			}
+		}
+		if (slot == ARRAY_SIZE(pint_irq_cfg)) {
+			/* No free IRQ slots */
+			return -EBUSY;
+		}
+		pin_pint_id[pin] = slot;
+	}
+	pint_irq_cfg[slot].used = true;
+	pint_irq_cfg[slot].pin = pin;
+	/* Attach pin to interrupt slot using INPUTMUX */
+	attach_pin_to_pint(pin, slot);
+	/* Now configure the interrupt. No need to install callback, this
+	 * driver handles the IRQ
+	 */
+	PINT_PinInterruptConfig(pint_base, slot, trigger, NULL);
+	return 0;
+}
+
+
+/**
+ * @brief disable PINT interrupt source.
+ *
+ * @param pin: pin interrupt source to disable
+ */
+void nxp_pint_pin_disable(uint8_t pin)
+{
+	uint8_t slot;
+
+	if (pin > ARRAY_SIZE(pin_pint_id)) {
+		return;
+	}
+
+	slot = pin_pint_id[pin];
+	if (slot == NO_PINT_ID) {
+		return;
+	}
+	/* Remove this pin from the PINT slot if one was in use */
+	pint_irq_cfg[slot].used = false;
+	PINT_PinInterruptConfig(pint_base, slot, kPINT_PinIntEnableNone, NULL);
+}
+
+/**
+ * @brief Install PINT callback
+ *
+ * @param pin: interrupt source to install callback for
+ * @param cb: callback to install
+ * @param data: user data to include in callback
+ * @return 0 on success, or negative value on error
+ */
+int nxp_pint_pin_set_callback(uint8_t pin, nxp_pint_cb_t cb, void *data)
+{
+	uint8_t slot;
+
+	if (pin > ARRAY_SIZE(pin_pint_id)) {
+		return -EINVAL;
+	}
+
+	slot = pin_pint_id[pin];
+	if (slot == NO_PINT_ID) {
+		return -EINVAL;
+	}
+
+	pint_irq_cfg[slot].callback = cb;
+	pint_irq_cfg[slot].user_data = data;
+	return 0;
+}
+
+/**
+ * @brief Remove PINT callback
+ *
+ * @param pin: interrupt source to remove callback for
+ */
+void nxp_pint_pin_unset_callback(uint8_t pin)
+{
+	uint8_t slot;
+
+	if (pin > ARRAY_SIZE(pin_pint_id)) {
+		return;
+	}
+
+	slot = pin_pint_id[pin];
+	if (slot == NO_PINT_ID) {
+		return;
+	}
+
+	pint_irq_cfg[slot].callback = NULL;
+}
+
+/* NXP PINT ISR handler- called with PINT slot ID */
+static void nxp_pint_isr(uint8_t *slot)
+{
+	PINT_PinInterruptClrStatus(pint_base, *slot);
+	if (pint_irq_cfg[*slot].used && pint_irq_cfg[*slot].callback) {
+		pint_irq_cfg[*slot].callback(pint_irq_cfg[*slot].pin,
+					pint_irq_cfg[*slot].user_data);
+	}
+}
+
+
+/* Defines PINT IRQ handler for a given irq index */
+#define NXP_PINT_IRQ(idx, node_id)						\
+	IF_ENABLED(DT_IRQ_HAS_IDX(node_id, idx),				\
+	(static uint8_t nxp_pint_idx_##idx = idx;				\
+	do {									\
+		IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, idx, irq),			\
+			    DT_IRQ_BY_IDX(node_id, idx, priority),		\
+			    nxp_pint_isr, &nxp_pint_idx_##idx, 0);		\
+		irq_enable(DT_IRQ_BY_IDX(node_id, idx, irq));			\
+	} while (false)))
+
+static int intc_nxp_pint_init(void)
+{
+	/* First, connect IRQs for each interrupt.
+	 * The IRQ handler will receive the PINT slot as a
+	 * parameter.
+	 */
+	LISTIFY(8, NXP_PINT_IRQ, (;), PINT_NODE);
+	PINT_Init(pint_base);
+	memset(pin_pint_id, NO_PINT_ID, ARRAY_SIZE(pin_pint_id));
+	return 0;
+}
+
+SYS_INIT(intc_nxp_pint_init, PRE_KERNEL_1,
+	CONFIG_INTC_INIT_PRIORITY);

dts/arm/nxp/nxp_lpc51u68.dtsi

@@ -57,7 +57,6 @@
 		gpio0: gpio@0 {
 			compatible = "nxp,lpc-gpio";
 			reg = <0x4008c000 0x2484>;
-			interrupts = <4 2>,<5 2>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			port = <0>;
@@ -66,12 +65,22 @@
 		gpio1: gpio@1 {
 			compatible = "nxp,lpc-gpio";
 			reg = <0x4008C000 0x2484>;
-			interrupts = <6 2>,<7 2>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			port = <1>;
 		};
 
+		pint: pint@4000 {
+			compatible = "nxp,pint";
+			reg = <0x4000 0x1000>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			interrupts = <4 2>, <5 2>, <6 2>, <7 2>;
+			num-lines = <4>;
+			num-inputs = <64>;
+		};
+
 		flexcomm0: flexcomm@40086000 {
 			compatible = "nxp,lpc-flexcomm";
 			reg = <0x40086000 0x1000>;

dts/arm/nxp/nxp_lpc54xxx.dtsi

@@ -112,7 +112,6 @@
 		gpio0: gpio@0 {
 			compatible = "nxp,lpc-gpio";
 			reg = <0x4008c000 0x2488>;
-			interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			port = <0>;
@@ -121,12 +120,23 @@
 		gpio1: gpio@1 {
 			compatible = "nxp,lpc-gpio";
 			reg = <0x4008C000 0x2488>;
-			interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			port = <1>;
 		};
 
+		pint: pint@4000 {
+			compatible = "nxp,pint";
+			reg = <0x4000 0x1000>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
+				<32 2>, <33 2>, <34 2>, <35 2>;
+			num-lines = <8>;
+			num-inputs = <64>;
+		};
+
 		mailbox0:mailbox@4008b000 {
 			compatible = "nxp,lpc-mailbox";
 			reg = <0x4008b000 0xEC>;

dts/arm/nxp/nxp_lpc55S0x_common.dtsi

@@ -116,7 +116,6 @@
 	gpio0: gpio@0 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x2488>;
-		interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <0>;
@@ -125,12 +124,23 @@
 	gpio1: gpio@1 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x2488>;
-		interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <1>;
 	};
 
+	pint: pint@4000 {
+		compatible = "nxp,pint";
+		reg = <0x4000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <0>;
+		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
+			<32 2>, <33 2>, <34 2>, <35 2>;
+		num-lines = <8>;
+		num-inputs = <64>;
+	};
+
 	flexcomm0: flexcomm@86000 {
 		compatible = "nxp,lpc-flexcomm";
 		reg = <0x86000 0x1000>;

dts/arm/nxp/nxp_lpc55S1x_common.dtsi

@@ -120,7 +120,6 @@
 	gpio0: gpio@0 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x2488>;
-		interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <0>;
@@ -129,12 +128,23 @@
 	gpio1: gpio@1 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x2488>;
-		interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <1>;
 	};
 
+	pint: pint@4000 {
+		compatible = "nxp,pint";
+		reg = <0x4000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <0>;
+		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
+			<32 2>, <33 2>, <34 2>, <35 2>;
+		num-lines = <8>;
+		num-inputs = <64>;
+	};
+
 	flexcomm0: flexcomm@86000 {
 		compatible = "nxp,lpc-flexcomm";
 		reg = <0x86000 0x1000>;

dts/arm/nxp/nxp_lpc55S2x_common.dtsi

@@ -127,7 +127,6 @@
 	gpio0: gpio@0 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x2488>;
-		interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <0>;
@@ -136,12 +135,23 @@
 	gpio1: gpio@1 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x2488>;
-		interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <1>;
 	};
 
+	pint: pint@4000 {
+		compatible = "nxp,pint";
+		reg = <0x4000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <0>;
+		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
+			<32 2>, <33 2>, <34 2>, <35 2>;
+		num-lines = <8>;
+		num-inputs = <64>;
+	};
+
 	dma0: dma-controller@82000 {
 		compatible = "nxp,lpc-dma";
 		reg = <0x82000 0x1000>;

dts/arm/nxp/nxp_lpc55S3x_common.dtsi

@@ -123,7 +123,6 @@
 	gpio0: gpio@0 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x278c>;
-		interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <0>;
@@ -132,7 +131,6 @@
 	gpio1: gpio@1 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x278c>;
-		interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <1>;
@@ -141,12 +139,23 @@
 	gpio2: gpio@2 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x278c>;
-		#interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <2>;
 	};
 
+	pint: pint@4000 {
+		compatible = "nxp,pint";
+		reg = <0x4000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <0>;
+		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
+			<32 2>, <33 2>, <34 2>, <35 2>;
+		num-lines = <8>;
+		num-inputs = <64>;
+	};
+
 	flexcomm0: flexcomm@86000 {
 		compatible = "nxp,lpc-flexcomm";
 		reg = <0x86000 0x1000>;

dts/arm/nxp/nxp_lpc55S6x_common.dtsi

@@ -146,7 +146,6 @@
 	gpio0: gpio@0 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x2488>;
-		interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <0>;
@@ -155,12 +154,23 @@
 	gpio1: gpio@1 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x2488>;
-		interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <1>;
 	};
 
+	pint: pint@4000 {
+		compatible = "nxp,pint";
+		reg = <0x4000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <0>;
+		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
+			<32 2>, <33 2>, <34 2>, <35 2>;
+		num-lines = <8>;
+		num-inputs = <64>;
+	};
+
 	dma0: dma-controller@82000 {
 		compatible = "nxp,lpc-dma";
 		reg = <0x82000 0x1000>;

dts/arm/nxp/nxp_rt5xx_common.dtsi

@@ -98,7 +98,6 @@
 	gpio0: gpio@0 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x100000 0x1000>;
-		interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <0>;
@@ -107,7 +106,6 @@
 	gpio1: gpio@1 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x100000 0x1000>;
-		interrupts = <35 2>,<36 2>,<37 2>,<38 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <1>;
@@ -153,6 +151,18 @@
 		port = <6>;
 	};
 
+	pint: pint@25000 {
+		compatible = "nxp,pint";
+		reg = <0x25000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <0>;
+		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
+			<35 2>, <36 2>, <37 2>, <38 2>;
+		num-lines = <8>;
+		num-inputs = <64>;
+	};
+
 	flexcomm0: flexcomm@106000 {
 		compatible = "nxp,lpc-flexcomm";
 		reg = <0x106000 0x1000>;

dts/arm/nxp/nxp_rt6xx_common.dtsi

@@ -97,7 +97,6 @@
 	gpio0: gpio@0 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x100000 0x1000>;
-		interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <0>;
@@ -106,7 +105,6 @@
 	gpio1: gpio@1 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x100000 0x1000>;
-		interrupts = <35 2>,<36 2>,<37 2>,<38 2>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		port = <1>;
@@ -144,6 +142,18 @@
 		port = <7>;
 	};
 
+	pint: pint@25000 {
+		compatible = "nxp,pint";
+		reg = <0x25000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <0>;
+		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
+			<35 2>, <36 2>, <37 2>, <38 2>;
+		num-lines = <8>;
+		num-inputs = <64>;
+	};
+
 	flexcomm0: flexcomm@106000 {
 		compatible = "nxp,lpc-flexcomm";
 		reg = <0x106000 0x1000>;

dts/bindings/interrupt-controller/nxp,pint.yaml

@@ -0,0 +1,24 @@
+description: NXP Pin interrupt and pattern match engine (PINT)
+
+compatible: "nxp,pint"
+
+include: [base.yaml, interrupt-controller.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  num-lines:
+    type: int
+    required: true
+    description: Number of interrupt lines supported by the interrupt controller.
+
+  num-inputs:
+    type: int
+    required: true
+    description: |
+      Number of inputs available to the PINT engine. These inputs are typically
+      GPIO pins.

include/zephyr/drivers/interrupt_controller/nxp_pint.h

@@ -0,0 +1,82 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Driver for Pin interrupt and pattern match engine in NXP MCUs
+ *
+ * The Pin interrupt and pattern match engine (PINT) supports
+ * sourcing inputs from any pins on GPIO ports 0 and 1 of NXP MCUs
+ * featuring the module, and generating interrupts based on these inputs.
+ * Pin inputs can generate separate interrupts to the NVIC, or be combined
+ * using the PINT's boolean logic based pattern match engine.
+ * This driver currently only supports the pin interrupt feature of
+ * the PINT.
+ */
+
+#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_NXP_PINT_H_
+#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_NXP_PINT_H_
+
+#include <fsl_pint.h>
+
+/**
+ * @brief Pin interrupt sources
+ *
+ * Pin interrupt sources available for use.
+ */
+enum nxp_pint_trigger {
+	/* Do not generate Pin Interrupt */
+	NXP_PINT_NONE = kPINT_PinIntEnableNone,
+	/* Generate Pin Interrupt on rising edge */
+	NXP_PINT_RISING  = kPINT_PinIntEnableRiseEdge,
+	/* Generate Pin Interrupt on falling edge */
+	NXP_PINT_FALLING  = kPINT_PinIntEnableFallEdge,
+	/* Generate Pin Interrupt on both edges */
+	NXP_PINT_BOTH = kPINT_PinIntEnableBothEdges,
+	/* Generate Pin Interrupt on low level */
+	NXP_PINT_LOW  = kPINT_PinIntEnableLowLevel,
+	/* Generate Pin Interrupt on high level */
+	NXP_PINT_HIGH = kPINT_PinIntEnableHighLevel
+};
+
+/* Callback for NXP PINT interrupt */
+typedef void (*nxp_pint_cb_t) (uint8_t pin, void *user);
+
+/**
+ * @brief Enable PINT interrupt source.
+ *
+ * @param pin: pin to use as interrupt source
+ *     0-64, corresponding to GPIO0 pin 1 - GPIO1 pin 31)
+ * @param trigger: one of nxp_pint_trigger flags
+ */
+int nxp_pint_pin_enable(uint8_t pin, enum nxp_pint_trigger trigger);
+
+
+/**
+ * @brief disable PINT interrupt source.
+ *
+ * @param pin: pin interrupt source to disable
+ */
+void nxp_pint_pin_disable(uint8_t pin);
+
+/**
+ * @brief Install PINT callback
+ *
+ * @param pin: interrupt source to install callback for
+ * @param cb: callback to install
+ * @param data: user data to include in callback
+ * @return 0 on success, or negative value on error
+ */
+int nxp_pint_pin_set_callback(uint8_t pin, nxp_pint_cb_t cb, void *data);
+
+/**
+ * @brief Remove PINT callback
+ *
+ * @param pin: interrupt source to remove callback for
+ */
+void nxp_pint_pin_unset_callback(uint8_t pin);
+
+
+#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_NXP_PINT_H_ */

west.yml

@@ -93,7 +93,7 @@ manifest:
       groups:
         - hal
     - name: hal_nxp
-      revision: d3c964cd854e53d55d21532431ee337d55348d8c
+      revision: f41cf88971505257e7f4798d845699da3fdc36d0
       path: modules/hal/nxp
       groups:
         - hal