boards: imx93_evk: add M33 DDR code support

This commit adds the support for running
the Cortex M33 code from DDR memory.

Signed-off-by: Alexandru Lastur <alexandru.lastur@nxp.com>
This commit is contained in:
Alexandru Lastur 2024-10-17 11:04:16 +03:00 committed by Benjamin Cabé
parent 72c4700d65
commit 72d8bb48e3
6 changed files with 68 additions and 1 deletions

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@ -3,5 +3,5 @@
config BOARD_IMX93_EVK
select SOC_MIMX9352_A55 if BOARD_IMX93_EVK_MIMX9352_A55
select SOC_MIMX9352_M33 if BOARD_IMX93_EVK_MIMX9352_M33
select SOC_MIMX9352_M33 if BOARD_IMX93_EVK_MIMX9352_M33 || BOARD_IMX93_EVK_MIMX9352_M33_DDR
select SOC_PART_NUMBER_MIMX9352DVVXM

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@ -4,3 +4,6 @@ board:
vendor: nxp
socs:
- name: mimx9352
variants:
- name: ddr
cpucluster: m33

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@ -240,10 +240,26 @@ prompt.
Use U-Boot to load and kick zephyr.bin to Cortex-M33 Core:
Boot with code from TCM
=======================
.. code-block:: console
load mmc 1:1 0x80000000 zephyr.bin;cp.b 0x80000000 0x201e0000 0x30000;bootaux 0x1ffe0000 0
Boot with code from DDR
=======================
.. code-block:: console
load mmc 1:1 0x84000000 zephyr.bin;dcache flush;bootaux 0x84000000 0
Note: Cortex M33 need execute permission to run code from DDR memory. In order
to enable this, `imx-atf`_ can to be modified in "plat/imx/imx93/trdc_config.h".
.. _imx-atf:
https://github.com/nxp-imx/imx-atf
Use this configuration to run basic Zephyr applications and kernel tests,
for example, with the :zephyr:code-sample:`synchronization` sample:

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@ -0,0 +1,23 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include "imx93_evk_mimx9352_m33.dts"
/ {
model = "NXP i.MX93 EVK board DDR variant";
chosen {
zephyr,sram = &ddr;
/delete-property/ zephyr,flash;
};
ddr: memory@84000000 {
device_type = "memory";
reg = <0x84000000 DT_SIZE_M(4)>;
};
};

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@ -0,0 +1,16 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
identifier: imx93_evk/mimx9352/m33/ddr
name: NXP i.MX93 EVK M33 DDR
type: mcu
arch: arm
toolchain:
- zephyr
- cross-compile
ram: 4096
flash: 0
supported:
- gpio
- uart
vendor: nxp

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@ -0,0 +1,9 @@
# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
CONFIG_CLOCK_CONTROL=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_XIP=n