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dts: riscv: add Telink B91 SPI driver support

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Added SPI driver DTSI support for Telink B91 platform.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
This commit is contained in:
Yuriy Vynnychek 2021-08-05 12:15:47 +03:00 committed by Christopher Friedt
parent d2ddd379c9
commit 77df331cc2
2 changed files with 151 additions and 8 deletions
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56
dts/bindings/spi/telink,b91-spi.yaml Normal file
View file

@ -0,0 +1,56 @@
# Copyright (c) 2021, Telink Semiconductor
# SPDX-License-Identifier: Apache-2.0
description: Telink B91 SPI
include: spi-controller.yaml
compatible: "telink,b91-spi"
properties:
reg:
required: true
peripheral-id:
type: string
required: true
enum:
- "PSPI_MODULE"
- "HSPI_MODULE"
pinctrl-0:
type: phandles
required: true
cs0-pin:
type: string
required: true
enum:
- "0"
- "PSPI_CSN_PC4"
- "PSPI_CSN_PC0"
- "PSPI_CSN_PD0"
- "HSPI_CSN_PA1"
- "HSPI_CSN_PB6"
cs1-pin:
type: string
required: false
enum:
- "0"
- "PSPI_CSN_PC4"
- "PSPI_CSN_PC0"
- "PSPI_CSN_PD0"
- "HSPI_CSN_PA1"
- "HSPI_CSN_PB6"
cs2-pin:
type: string
required: false
enum:
- "0"
- "PSPI_CSN_PC4"
- "PSPI_CSN_PC0"
- "PSPI_CSN_PD0"
- "HSPI_CSN_PA1"
- "HSPI_CSN_PB6"

103
dts/riscv/telink_b91.dtsi
View file

@ -170,6 +170,32 @@
#pwm-cells = <2>;
};
hspi: spi@81FFFFC0 {
compatible = "telink,b91-spi";
label = "HSPI";
reg = <0x81FFFFC0 0x40>;
peripheral-id = "HSPI_MODULE";
cs0-pin = "0";
cs1-pin = "0";
cs2-pin = "0";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pspi: spi@80140040 {
compatible = "telink,b91-spi";
label = "PSPI";
reg = <0x80140040 0x40>;
peripheral-id = "PSPI_MODULE";
cs0-pin = "0";
cs1-pin = "0";
cs2-pin = "0";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pinmux: pinmux@80140330 {
compatible = "telink,b91-pinmux";
reg = <0x80140330 0x28
@ -181,7 +207,7 @@
label = "pinmux";
status = "disabled";
/* Define UART0 pins: TX(PA3 PB2 PD2), RX(PA4 PB3 PD3) */
/* UART0: TX(PA3 PB2 PD2), RX(PA4 PB3 PD3) */
uart0_tx_pa3: uart0_tx_pa3 {
pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_A, B91_PIN_3)>;
@ -203,7 +229,7 @@
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_D, B91_PIN_3)>;
};
/* Define UART1 pins: TX(PC6 PD6 PE0), RX(PC7 PD7 PE2) */
/* UART1: TX(PC6 PD6 PE0), RX(PC7 PD7 PE2) */
uart1_tx_pc6: uart1_tx_pc6 {
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_C, B91_PIN_6)>;
@ -225,7 +251,7 @@
pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_E, B91_PIN_2)>;
};
/* Define PWM Channel 0 pins (PB4, PC0, PE3) */
/* PWM Channel 0 (PB4, PC0, PE3) */
pwm_ch0_pb4: pwm_ch0_pb4 {
pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_B, B91_PIN_4)>;
@ -237,7 +263,7 @@
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_E, B91_PIN_3)>;
};
/* Define PWM Channel 1 pins (PB5, PE1) */
/* PWM Channel 1 (PB5, PE1) */
pwm_ch1_pb5: pwm_ch1_pb5 {
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_B, B91_PIN_5)>;
@ -246,7 +272,7 @@
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_E, B91_PIN_1)>;
};
/* Define PWM Channel 2 pins (PB7, PE2) */
/* PWM Channel 2 (PB7, PE2) */
pwm_ch2_pb7: pwm_ch2_pb7 {
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_B, B91_PIN_7)>;
@ -255,7 +281,7 @@
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_E, B91_PIN_2)>;
};
/* Define PWM Channel 3 pins (PB1, PE0) */
/* PWM Channel 3 (PB1, PE0) */
pwm_ch3_pb1: pwm_ch3_pb1 {
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_B, B91_PIN_1)>;
@ -264,7 +290,7 @@
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_E, B91_PIN_0)>;
};
/* Define PWM Channel 4 pins (PD7, PE4) */
/* PWM Channel 4 (PD7, PE4) */
pwm_ch4_pd7: pwm_ch4_pd7 {
pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_D, B91_PIN_7)>;
@ -273,7 +299,7 @@
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_E, B91_PIN_4)>;
};
/* Define PWM Channel 5 pins (PB0, PE5) */
/* PWM Channel 5 (PB0, PE5) */
pwm_ch5_pb0: pwm_ch5_pb0 {
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_B, B91_PIN_0)>;
@ -281,6 +307,67 @@
pwm_ch5_pe5: pwm_ch5_pe5 {
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_E, B91_PIN_5)>;
};
/* PSPI: CLK(PC5, PB5, PD1), MOSI(PC7, PB7, PD3), MISO(PC6, PB6, PD2) */
pspi_clk_pc5: pspi_clk_pc5 {
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_C, B91_PIN_5)>;
};
pspi_mosi_io0_pc7: pspi_mosi_io0_pc7 {
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_C, B91_PIN_7)>;
};
pspi_miso_io1_pc6: pspi_miso_io1_pc6 {
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_C, B91_PIN_6)>;
};
pspi_clk_pb5: pspi_clk_pb5 {
pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_B, B91_PIN_5)>;
};
pspi_mosi_io0_pb7: pspi_mosi_io0_pb7 {
pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_B, B91_PIN_7)>;
};
pspi_miso_io1_pb6: pspi_miso_io1_pb6 {
pinmux = <B91_PINMUX_SET(B91_FUNC_B, B91_PORT_B, B91_PIN_6)>;
};
pspi_clk_pd1: pspi_clk_pd1 {
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_D, B91_PIN_1)>;
};
pspi_mosi_io0_pd3: pspi_mosi_io0_pd3 {
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_D, B91_PIN_3)>;
};
pspi_miso_io1_pd2: pspi_miso_io1_pd2 {
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_D, B91_PIN_2)>;
};
/* HSPI: CLK(PA2, PB4), MOSI(PA4, PB3), MISO(PA3, PB2) */
hspi_clk_pa2: hspi_clk_pa2 {
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_A, B91_PIN_2)>;
};
hspi_mosi_io0_pa4: hspi_mosi_io0_pa4 {
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_A, B91_PIN_4)>;
};
hspi_miso_io1_pa3: hspi_miso_io1_pa3 {
pinmux = <B91_PINMUX_SET(B91_FUNC_C, B91_PORT_A, B91_PIN_3)>;
};
hspi_clk_pb4: hspi_clk_pb4 {
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_B, B91_PIN_4)>;
};
hspi_mosi_io0_pb3: hspi_mosi_io0_pb3 {
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_B, B91_PIN_3)>;
};
hspi_miso_io1_pb2: hspi_miso_io1_pb2 {
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_B, B91_PIN_2)>;
};
hspi_io2_pb1: hspi_io2_pb1 {
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_B, B91_PIN_1)>;
};
hspi_io3_pb0: hspi_io3_pb0 {
pinmux = <B91_PINMUX_SET(B91_FUNC_A, B91_PORT_B, B91_PIN_0)>;
};
};
};
};