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drivers: intc: esp32c2: Added support

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Added support for ESP32C2 and ESP8684

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This commit is contained in:
Raffael Rostagno 2024-07-24 13:52:05 -03:00 committed by Anas Nashif
parent 782ccf2e99
commit 78832ab78f
5 changed files with 213 additions and 3 deletions
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2
drivers/interrupt_controller/Kconfig.esp32
View file

@ -7,7 +7,7 @@ config INTC_ESP32
bool "Interrupt allocator for Xtensa-based Espressif SoCs"
default y
depends on SOC_FAMILY_ESPRESSIF_ESP32
depends on !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
depends on !SOC_SERIES_ESP32C2 && !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
help
Enable custom interrupt allocator for Espressif SoCs based on Xtensa
architecture.

2
drivers/interrupt_controller/Kconfig.esp32c3
View file

@ -4,7 +4,7 @@
config INTC_ESP32C3
bool "ESP32C3 interrupt controller driver"
depends on SOC_FAMILY_ESPRESSIF_ESP32
depends on SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
default y
help
Enables the esp32c3 interrupt controller driver to handle ISR

2
drivers/interrupt_controller/intc_esp32c3.c
View file

@ -68,7 +68,7 @@ static uint8_t esp_intr_irq_alloc[ESP32C6_INTC_AVAILABLE_IRQS][ESP32C6_INTC_SRCS
static uint32_t esp_intr_enabled_mask[STATUS_MASK_NUM] = {0, 0, 0};
#if defined(CONFIG_SOC_SERIES_ESP32C3)
#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
static uint32_t esp_intr_find_irq_for_source(uint32_t source)
{

54
include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h Normal file
View file

@ -0,0 +1,54 @@
/*
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C2_INTMUX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C2_INTMUX_H_
#define WIFI_MAC_INTR_SOURCE 0
#define WIFI_MAC_NMI_SOURCE 1
#define WIFI_PWR_INTR_SOURCE 2
#define WIFI_BB_INTR_SOURCE 3
#define BT_MAC_INTR_SOURCE 4
#define BT_BB_INTR_SOURCE 5
#define BT_BB_NMI_SOURCE 6
#define LP_TIMER_SOURCE 7
#define COEX_SOURCE 8
#define BLE_TIMER_SOURCE 9
#define BLE_SEC_SOURCE 10
#define I2C_MASTER_SOURCE 11
#define APB_CTRL_INTR_SOURCE 12
#define GPIO_INTR_SOURCE 13
#define GPIO_NMI_SOURCE 14
#define SPI1_INTR_SOURCE 15
#define SPI2_INTR_SOURCE 16
#define UART0_INTR_SOURCE 17
#define UART1_INTR_SOURCE 18
#define LEDC_INTR_SOURCE 19
#define EFUSE_INTR_SOURCE 20
#define RTC_CORE_INTR_SOURCE 21
#define I2C_EXT0_INTR_SOURCE 22
#define TG0_T0_LEVEL_INTR_SOURCE 23
#define TG0_WDT_LEVEL_INTR_SOURCE 24
#define CACHE_IA_INTR_SOURCE 25
#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 26
#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 27
#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 28
#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 29
#define ICACHE_PRELOAD0_INTR_SOURCE 30
#define ICACHE_SYNC0_INTR_SOURCE 31
#define APB_ADC_INTR_SOURCE 32
#define DMA_CH0_INTR_SOURCE 33
#define SHA_INTR_SOURCE 34
#define ECC_INTR_SOURCE 35
#define FROM_CPU_INTR0_SOURCE 36
#define FROM_CPU_INTR1_SOURCE 37
#define FROM_CPU_INTR2_SOURCE 38
#define FROM_CPU_INTR3_SOURCE 39
#define ASSIST_DEBUG_INTR_SOURCE 40
#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 41
#define CACHE_CORE0_ACS_INTR_SOURCE 42
#endif

156
include/zephyr/dt-bindings/pinctrl/esp32c2-gpio-sigmap.h Normal file
View file

@ -0,0 +1,156 @@
/*
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_
#define ESP_NOSIG ESP_SIG_INVAL
#define ESP_SPICLK_OUT_MUX ESP_SPICLK_OUT
#define ESP_SPIQ_IN 0
#define ESP_SPIQ_OUT 0
#define ESP_SPID_IN 1
#define ESP_SPID_OUT 1
#define ESP_SPIHD_IN 2
#define ESP_SPIHD_OUT 2
#define ESP_SPIWP_IN 3
#define ESP_SPIWP_OUT 3
#define ESP_SPICLK_OUT 4
#define ESP_SPICS0_OUT 5
#define ESP_U0RXD_IN 6
#define ESP_U0TXD_OUT 6
#define ESP_U0CTS_IN 7
#define ESP_U0RTS_OUT 7
#define ESP_U0DSR_IN 8
#define ESP_U0DTR_OUT 8
#define ESP_U1RXD_IN 9
#define ESP_U1TXD_OUT 9
#define ESP_U1CTS_IN 10
#define ESP_U1RTS_OUT 10
#define ESP_U1DSR_IN 11
#define ESP_U1DTR_OUT 11
#define ESP_SPIQ_MONITOR 15
#define ESP_SPID_MONITOR 16
#define ESP_SPIHD_MONITOR 17
#define ESP_SPIWP_MONITOR 18
#define ESP_SPICS1_OUT 19
#define ESP_CPU_TESTBUS0 20
#define ESP_CPU_TESTBUS1 21
#define ESP_CPU_TESTBUS2 22
#define ESP_CPU_TESTBUS3 23
#define ESP_CPU_TESTBUS4 24
#define ESP_CPU_TESTBUS5 25
#define ESP_CPU_TESTBUS6 26
#define ESP_CPU_TESTBUS7 27
#define ESP_CPU_GPIO_IN0 28
#define ESP_CPU_GPIO_OUT0 28
#define ESP_CPU_GPIO_IN1 29
#define ESP_CPU_GPIO_OUT1 29
#define ESP_CPU_GPIO_IN2 30
#define ESP_CPU_GPIO_OUT2 30
#define ESP_CPU_GPIO_IN3 31
#define ESP_CPU_GPIO_OUT3 31
#define ESP_CPU_GPIO_IN4 32
#define ESP_CPU_GPIO_OUT4 32
#define ESP_CPU_GPIO_IN5 33
#define ESP_CPU_GPIO_OUT5 33
#define ESP_CPU_GPIO_IN6 34
#define ESP_CPU_GPIO_OUT6 34
#define ESP_CPU_GPIO_IN7 35
#define ESP_CPU_GPIO_OUT7 35
#define ESP_EXT_ADC_START 45
#define ESP_LEDC_LS_SIG_OUT0 45
#define ESP_LEDC_LS_SIG_OUT1 46
#define ESP_LEDC_LS_SIG_OUT2 47
#define ESP_LEDC_LS_SIG_OUT3 48
#define ESP_LEDC_LS_SIG_OUT4 49
#define ESP_LEDC_LS_SIG_OUT5 50
#define ESP_RMT_SIG_IN0 51
#define ESP_RMT_SIG_OUT0 51
#define ESP_RMT_SIG_IN1 52
#define ESP_RMT_SIG_OUT1 52
#define ESP_I2CEXT0_SCL_IN 53
#define ESP_I2CEXT0_SCL_OUT 53
#define ESP_I2CEXT0_SDA_IN 54
#define ESP_I2CEXT0_SDA_OUT 54
#define ESP_FSPICLK_IN 63
#define ESP_FSPICLK_OUT 63
#define ESP_FSPIQ_IN 64
#define ESP_FSPIQ_OUT 64
#define ESP_FSPID_IN 65
#define ESP_FSPID_OUT 65
#define ESP_FSPIHD_IN 66
#define ESP_FSPIHD_OUT 66
#define ESP_FSPIWP_IN 67
#define ESP_FSPIWP_OUT 67
#define ESP_FSPICS0_IN 68
#define ESP_FSPICS0_OUT 68
#define ESP_FSPICS1_OUT 69
#define ESP_FSPICS2_OUT 70
#define ESP_FSPICS3_OUT 71
#define ESP_FSPICS4_OUT 72
#define ESP_FSPICS5_OUT 73
#define ESP_EXTERN_PRIORITY_I 77
#define ESP_EXTERN_PRIORITY_O 77
#define ESP_EXTERN_ACTIVE_I 78
#define ESP_EXTERN_ACTIVE_O 78
#define ESP_GPIO_EVENT_MATRIX_IN0 79
#define ESP_GPIO_TASK_MATRIX_OUT0 79
#define ESP_GPIO_EVENT_MATRIX_IN1 80
#define ESP_GPIO_TASK_MATRIX_OUT1 80
#define ESP_GPIO_EVENT_MATRIX_IN2 81
#define ESP_GPIO_TASK_MATRIX_OUT2 81
#define ESP_GPIO_EVENT_MATRIX_IN3 82
#define ESP_GPIO_TASK_MATRIX_OUT3 82
#define ESP_BB_DIAG8_OUT 83
#define ESP_BB_DIAG9_OUT 84
#define ESP_BB_DIAG10_OUT 85
#define ESP_BB_DIAG11_OUT 86
#define ESP_BB_DIAG12_OUT 87
#define ESP_BB_DIAG13_OUT 88
#define ESP_ANT_SEL0 89
#define ESP_ANT_SEL1 90
#define ESP_ANT_SEL2 91
#define ESP_ANT_SEL3 92
#define ESP_ANT_SEL4 93
#define ESP_ANT_SEL5 94
#define ESP_ANT_SEL6 95
#define ESP_ANT_SEL7 96
#define ESP_SIG_IN_FUNC_97 97
#define ESP_SIG_IN_FUNC97 97
#define ESP_SIG_IN_FUNC_98 98
#define ESP_SIG_IN_FUNC98 98
#define ESP_SIG_IN_FUNC_99 99
#define ESP_SIG_IN_FUNC99 99
#define ESP_SIG_IN_FUNC_100 100
#define ESP_SIG_IN_FUNC100 100
#define ESP_BLE_DBG_SYNCERR 101
#define ESP_BLE_DBG_SYNC_FOUND 102
#define ESP_BLE_DBG_CH_IDX 103
#define ESP_BLE_DBG_SYNC_WINDOW 104
#define ESP_BLE_DBG_DATA_EN 105
#define ESP_BLE_DBG_DATA 106
#define ESP_BLE_DBG_PKT_TX_ON 107
#define ESP_BLE_DBG_PKT_RX_ON 108
#define ESP_BLE_DBG_TXRU_ON 109
#define ESP_BLE_DBG_RXRU_ON 110
#define ESP_BLE_DBG_LELC_ST0 111
#define ESP_BLE_DBG_LELC_ST1 112
#define ESP_BLE_DBG_LELC_ST2 113
#define ESP_BLE_DBG_LELC_ST3 114
#define ESP_BLE_DBG_CRCOK 115
#define ESP_BLE_DBG_CLK_GPIO 116
#define ESP_BLE_DBG_RADIO_START 117
#define ESP_BLE_DBG_SEQUENCE_ON 118
#define ESP_BLE_DBG_COEX_BT_ON 119
#define ESP_BLE_DBG_COEX_WIFI_ON 120
#define ESP_CLK_OUT_OUT1 123
#define ESP_CLK_OUT_OUT2 124
#define ESP_CLK_OUT_OUT3 125
#define ESP_SIG_GPIO_OUT 128
#define ESP_GPIO_MAP_DATE 0x2106190
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_ */