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arch: arm: cortex_m: Revert "enable armv8m.baseline to use BASEPRI"

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This reverts commit 0781a86862.
BASEPRI is only functionnal if mainline extension is present.
If not, it is "RES0". See: Arm®v8-M Architecture Reference Manual D1.2.5.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This commit is contained in:
Wilfried Chauveau 2023-10-23 16:26:16 +01:00 committed by Carles Cufí
parent 3de98643ed
commit 7a216d2a69
1 changed files with 6 additions and 14 deletions
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20
include/zephyr/arch/arm/asm_inline_gcc.h
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@ -43,8 +43,8 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
{ {
unsigned int key; unsigned int key;
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && !defined(CONFIG_ARMV8_M_BASELINE) #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#if CONFIG_MP_MAX_NUM_CPUS == 1 #if CONFIG_MP_MAX_NUM_CPUS == 1 || defined(CONFIG_ARMV8_M_BASELINE)
__asm__ volatile("mrs %0, PRIMASK;" __asm__ volatile("mrs %0, PRIMASK;"
"cpsid i" "cpsid i"
: "=r" (key) : "=r" (key)
@ -53,7 +53,7 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
#else #else
#error "Cortex-M0 and Cortex-M0+ require SoC specific support for cross core synchronisation." #error "Cortex-M0 and Cortex-M0+ require SoC specific support for cross core synchronisation."
#endif #endif
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV8_M_BASELINE) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
unsigned int tmp; unsigned int tmp;
__asm__ volatile( __asm__ volatile(
@ -61,15 +61,7 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
"mrs %0, BASEPRI;" "mrs %0, BASEPRI;"
"msr BASEPRI_MAX, %1;" "msr BASEPRI_MAX, %1;"
"isb;" "isb;"
: "=r"(key), : "=r"(key), "=r"(tmp)
#if defined(CONFIG_ARMV8_M_BASELINE)
/* armv8-m.baseline's mov is limited to registers r0-r7.
* Let the compiler know we have this constraint on tmp.
*/
"=l"(tmp)
#else
"=r"(tmp)
#endif
: "i"(_EXC_IRQ_DEFAULT_PRIO) : "i"(_EXC_IRQ_DEFAULT_PRIO)
: "memory"); : "memory");
#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \ #elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
@ -95,7 +87,7 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key) static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
{ {
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && !defined(CONFIG_ARMV8_M_BASELINE) #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
if (key != 0U) { if (key != 0U) {
return; return;
} }
@ -103,7 +95,7 @@ static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
"cpsie i;" "cpsie i;"
"isb" "isb"
: : : "memory"); : : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV8_M_BASELINE) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
__asm__ volatile( __asm__ volatile(
"msr BASEPRI, %0;" "msr BASEPRI, %0;"
"isb;" "isb;"