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ITE: dts: it8xxx2: Add the option of 512k flash size

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Add the option of 512k flash size.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2022-11-23 18:58:07 +08:00 committed by Anas Nashif
parent 68d242de42
commit 7f3d61c608
3 changed files with 36 additions and 2 deletions
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26
dts/riscv/ite/it82202ax-512.dtsi Normal file
View file

@ -0,0 +1,26 @@
/*
* Copyright (c) 2023 ITE Corporation. All Rights Reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
/ {
soc {
flashctrl: flash-controller@f01000 {
compatible = "ite,it8xxx2-flash-controller";
reg = <0x00f01000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@80000000 {
compatible = "soc-nv-flash";
reg = <0x80000000 DT_SIZE_K(512)>;
erase-block-size = <4096>;
write-block-size = <4>;
};
};
};
};

4
soc/riscv/riscv-ite/common/vector.S
View file

@ -33,7 +33,7 @@ SECTION_FUNC(vectors, __start)
la t0, _isr_wrapper
csrw mtvec, t0
csrwi mie, 0
#if (CONFIG_SOC_IT8XXX2_FLASH_SIZE_BYTES == 0x100000)
/*
* bit[3-0]@EIDSR=8: instruction local memory size is 1M byte
* This operation must be done before accessing memory.
@ -43,7 +43,7 @@ SECTION_FUNC(vectors, __start)
andi t1, t1, 0xf0
ori t1, t1, 0x8
sb t1, 0(t0)
#endif
/* Jump to __initialize */
tail __initialize

8
soc/riscv/riscv-ite/it8xxx2/Kconfig.soc
View file

@ -141,4 +141,12 @@ config SOC_IT8XXX2_SHA256_HW_ACCELERATE
If we enable this config, because HW limits, the sha256 data must place in
first 4KB of RAM.
DT_CHOSEN_ZEPHYR_FLASH := zephyr,flash
config SOC_IT8XXX2_FLASH_SIZE_BYTES
hex
default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_ZEPHYR_FLASH))
help
Total size of writable flash.
endif # SOC_IT8XXX2