From 85aff8385ff3bbfc9520336a01f97695f0571b07 Mon Sep 17 00:00:00 2001 From: Qiang Zhang Date: Fri, 31 May 2024 11:24:13 +0800 Subject: [PATCH] dts: arm/nxp/mcxn94x: Add sai nodes for NXP mcxn94x Add sai nodes for NXP mcxn94x Signed-off-by: Qiang Zhang --- dts/arm/nxp/nxp_mcxn94x_common.dtsi | 33 +++++++++++++++++++++++++++++ dts/bindings/i2s/nxp,mcux-i2s.yaml | 6 +++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/dts/arm/nxp/nxp_mcxn94x_common.dtsi b/dts/arm/nxp/nxp_mcxn94x_common.dtsi index 1b9ef18153e..48e99586de5 100644 --- a/dts/arm/nxp/nxp_mcxn94x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxn94x_common.dtsi @@ -1040,6 +1040,39 @@ clock-src = <0>; alarms-count = <1>; }; + + sai0: sai@106000 { + compatible = "nxp,mcux-i2s"; + #address-cells = <1>; + #size-cells = <0>; + #pinmux-cells = <2>; + reg = < 0x106000 0x1000>; + clocks = <&syscon MCUX_SAI0_CLK>; + pinmuxes = <&sai0 0x100 0x40000000>; + interrupts = <59 0>; + dmas = <&edma0 0 99>, <&edma0 0 100>; + dma-names = "rx", "tx"; + nxp,tx-channel = <1>; + nxp,tx-dma-channel = <0>; + nxp,rx-dma-channel = <1>; + status = "disabled"; + }; + sai1: sai@107000 { + compatible = "nxp,mcux-i2s"; + #address-cells = <1>; + #size-cells = <0>; + #pinmux-cells = <2>; + reg = < 0x107000 0x1000>; + clocks = <&syscon MCUX_SAI1_CLK>; + pinmuxes = <&sai1 0x100 0x40000000>; + interrupts = <60 0>; + dmas = <&edma0 0 101>, <&edma0 0 102>; + dma-names = "rx", "tx"; + nxp,tx-channel = <1>; + nxp,tx-dma-channel = <2>; + nxp,rx-dma-channel = <3>; + status = "disabled"; + }; }; &systick { diff --git a/dts/bindings/i2s/nxp,mcux-i2s.yaml b/dts/bindings/i2s/nxp,mcux-i2s.yaml index 6aed4a4bf34..56239140e9a 100644 --- a/dts/bindings/i2s/nxp,mcux-i2s.yaml +++ b/dts/bindings/i2s/nxp,mcux-i2s.yaml @@ -1,4 +1,4 @@ -# Copyright 2021,2023 NXP +# Copyright 2021,2023-2024 NXP # SPDX-License-Identifier: Apache-2.0 description: NXP mcux SAI-I2S controller @@ -64,3 +64,7 @@ properties: clock-mux: type: int description: Clock mux source for SAI root clock + +pinmux-cells: + - pin + - function