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drivers: adc: gd32: use clock control API

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Use the clock control API to turn on ADC clocks. Note that clock
selection is not yet implemented, so we still rely on custom rcu
properties for that.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2022-09-03 19:06:28 +02:00 committed by Carles Cufí
parent 1c7138fbb1
commit 86654dbeae
6 changed files with 17 additions and 15 deletions
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10
drivers/adc/adc_gd32.c
View file

@ -7,6 +7,9 @@
#define DT_DRV_COMPAT gd_gd32_adc
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/reset.h>
@ -98,10 +101,10 @@ static const uint32_t table_samp_time[] = {
struct adc_gd32_config {
uint32_t reg;
uint32_t rcu_periph_clock;
#ifdef CONFIG_SOC_SERIES_GD32F3X0
uint32_t rcu_clock_source;
#endif
uint16_t clkid;
struct reset_dt_spec reset;
uint8_t channels;
const struct pinctrl_dev_config *pcfg;
@ -348,7 +351,8 @@ static int adc_gd32_init(const struct device *dev)
rcu_adc_clock_config(cfg->rcu_clock_source);
#endif
rcu_periph_clock_enable(cfg->rcu_periph_clock);
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&cfg->clkid);
(void)reset_line_toggle_dt(&cfg->reset);
@ -449,7 +453,7 @@ static void adc_gd32_global_irq_cfg(void)
}; \
const static struct adc_gd32_config adc_gd32_config_##n = { \
.reg = DT_INST_REG_ADDR(n), \
.rcu_periph_clock = DT_INST_PROP(n, rcu_periph_clock), \
.clkid = DT_INST_CLOCKS_CELL(n, id), \
.reset = RESET_DT_SPEC_INST_GET(n), \
.channels = DT_INST_PROP(n, channels), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \

2
dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi
View file

@ -80,8 +80,8 @@
compatible = "gd,gd32-adc";
reg = <0x40012400 0x400>;
interrupts = <12 0>;
rcu-periph-clock = <0x609>;
rcu-clock-source = <GD32_RCU_ADCCK_APB2_DIV4>;
clocks = <&cctl GD32_CLOCK_ADC>;
resets = <&rctl GD32_RESET_ADC>;
channels = <16>;
status = "disabled";

6
dts/arm/gigadevice/gd32f403/gd32f403.dtsi
View file

@ -148,7 +148,7 @@
compatible = "gd,gd32-adc";
reg = <0x40012400 0x400>;
interrupts = <18 0>;
rcu-periph-clock = <0x609>;
clocks = <&cctl GD32_CLOCK_ADC0>;
resets = <&rctl GD32_RESET_ADC0>;
channels = <16>;
status = "disabled";
@ -159,7 +159,7 @@
compatible = "gd,gd32-adc";
reg = <0x40012800 0x400>;
interrupts = <18 0>;
rcu-periph-clock = <0x60A>;
clocks = <&cctl GD32_CLOCK_ADC1>;
resets = <&rctl GD32_RESET_ADC1>;
channels = <16>;
status = "disabled";
@ -170,7 +170,7 @@
compatible = "gd,gd32-adc";
reg = <0x40013c00 0x400>;
interrupts = <47 0>;
rcu-periph-clock = <0x60F>;
clocks = <&cctl GD32_CLOCK_ADC2>;
resets = <&rctl GD32_RESET_ADC2>;
channels = <16>;
status = "disabled";

6
dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi
View file

@ -224,7 +224,7 @@
compatible = "gd,gd32-adc";
reg = <0x40012000 0x100>;
interrupts = <18 0>;
rcu-periph-clock = <0x1108>;
clocks = <&cctl GD32_CLOCK_ADC0>;
resets = <&rctl GD32_RESET_ADC0>;
channels = <16>;
status = "disabled";
@ -235,7 +235,7 @@
compatible = "gd,gd32-adc";
reg = <0x40012100 0x100>;
interrupts = <18 0>;
rcu-periph-clock = <0x1109>;
clocks = <&cctl GD32_CLOCK_ADC1>;
resets = <&rctl GD32_RESET_ADC1>;
channels = <16>;
status = "disabled";
@ -246,7 +246,7 @@
compatible = "gd,gd32-adc";
reg = <0x40012200 0x100>;
interrupts = <18 0>;
rcu-periph-clock = <0x110A>;
clocks = <&cctl GD32_CLOCK_ADC2>;
resets = <&rctl GD32_RESET_ADC2>;
channels = <16>;
status = "disabled";

4
dts/bindings/adc/gd,gd32-adc.yaml
View file

@ -25,9 +25,7 @@ properties:
resets:
required: true
rcu-periph-clock:
type: int
description: Reset Control Unit Peripheral Clock ID
clocks:
required: true
rcu-clock-source:

4
dts/riscv/gigadevice/gd32vf103.dtsi
View file

@ -118,7 +118,7 @@
compatible = "gd,gd32-adc";
reg = <0x40012400 0x400>;
interrupts = <37 0>;
rcu-periph-clock = <0x609>;
clocks = <&cctl GD32_CLOCK_ADC0>;
resets = <&rctl GD32_RESET_ADC0>;
channels = <16>;
status = "disabled";
@ -129,7 +129,7 @@
compatible = "gd,gd32-adc";
reg = <0x40012800 0x400>;
interrupts = <37 0>;
rcu-periph-clock = <0x60A>;
clocks = <&cctl GD32_CLOCK_ADC1>;
resets = <&rctl GD32_RESET_ADC1>;
channels = <16>;
status = "disabled";