soc: infineon: port Infineon SOC to HWMv2

Port Infineon SOC to HWMv2.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>

MAINTAINERS.yml

@@ -3706,8 +3706,6 @@ Infineon Platforms:
     - drivers/*/*xmc*
     - drivers/sensor/infineon/
     - dts/arm/infineon/
-    - dts/arm/cypress/
-    - soc/cypress/
     - dts/bindings/*/*infineon*
     - soc/infineon/
   labels:

drivers/hwinfo/Kconfig

@@ -173,7 +173,7 @@ config HWINFO_LITEX
 config HWINFO_PSOC6
 	bool "Cypress PSoC-6 unique device ID"
 	default y
-	depends on SOC_FAMILY_PSOC6
+	depends on SOC_FAMILY_PSOC6_LEGACY
 	help
 	  Enable Cypress PSoC-6 hwinfo driver.
 

modules/hal_infineon/CMakeLists.txt

@@ -2,7 +2,7 @@
 # Copyright (c) 2022 Cypress Semiconductor Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-if(CONFIG_HAS_XMCLIB OR CONFIG_SOC_FAMILY_PSOC6 OR CONFIG_SOC_FAMILY_INFINEON_CAT1)
+if(CONFIG_HAS_XMCLIB OR CONFIG_SOC_FAMILY_PSOC6_LEGACY OR CONFIG_SOC_FAMILY_INFINEON_CAT1)
   zephyr_library_named(modules_hal_infineon)
   zephyr_library_compile_options(-Wno-array-bounds)
 endif()
@@ -12,7 +12,7 @@ if (CONFIG_HAS_XMCLIB)
   add_subdirectory(${ZEPHYR_HAL_INFINEON_MODULE_DIR}/XMCLib XMCLib)
 endif()
 
-if (CONFIG_SOC_FAMILY_INFINEON_CAT1A OR CONFIG_SOC_FAMILY_PSOC6)
+if (CONFIG_SOC_FAMILY_INFINEON_CAT1 OR CONFIG_SOC_FAMILY_PSOC6_LEGACY)
   ## Add core-lib sources for CAT1 devices
   add_subdirectory(core-lib)
 
@@ -23,7 +23,7 @@ if (CONFIG_SOC_FAMILY_INFINEON_CAT1A OR CONFIG_SOC_FAMILY_PSOC6)
   add_subdirectory(mtb-template-cat1)
 endif()
 
-if (CONFIG_SOC_FAMILY_INFINEON_CAT1A)
+if (CONFIG_SOC_FAMILY_INFINEON_CAT1 AND NOT CONFIG_SOC_FAMILY_PSOC6_LEGACY)
   ## Add mtb-hal-cat1 sources for CAT1 devices
   add_subdirectory(mtb-hal-cat1)
 

modules/hal_infineon/Kconfig

@@ -4,7 +4,7 @@
 config ZEPHYR_HAL_INFINEON_MODULE
 	bool
 
-if SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1
+if SOC_FAMILY_INFINEON_CAT1 || SOC_FAMILY_PSOC6_LEGACY
 
 config USE_INFINEON_ADC
 	bool
@@ -77,8 +77,7 @@ config USE_INFINEON_FLASH
 	help
 	  Enable Flash HAL module driver for Infineon devices
 
-endif # SOC_FAMILY_PSOC6
+endif # SOC_FAMILY_INFINEON_CAT1 || SOC_FAMILY_PSOC6_LEGACY
-
 config USE_INFINEON_ABSTRACTION_RTOS
 	bool "Abstraction RTOS component (Zephyr support)"
 	help

modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt

@@ -29,8 +29,6 @@ zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_PSOC6_01_124_BGA
   ${hal_cat1a_dir}/source/pin_packages/cyhal_psoc6_01_124_bga.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_PSOC6_01_124_BGA_SIP
   ${hal_cat1a_dir}/source/pin_packages/cyhal_psoc6_01_124_bga_sip.c)
-zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_PSOC6_01_43_SMT
-  ${hal_cat1a_dir}/source/pin_packages/cyhal_psoc6_01_43_smt.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_PSOC6_01_68_QFN_BLE
   ${hal_cat1a_dir}/source/pin_packages/cyhal_psoc6_01_68_qfn_ble.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_PSOC6_01_80_WLCSP

modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt

@@ -7,8 +7,13 @@ set(pdl_dir             ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1)
 set(pdl_drv_dir         ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/drivers)
 set(pdl_dev_cat1a_dir   ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/devices/COMPONENT_CAT1A)
 
+
+# Generate PDL specific SOC defines
 zephyr_compile_definitions(${CONFIG_SOC_PART_NUMBER})
-zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 ${CONFIG_SOC})
+zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 $<UPPER_CASE:${CONFIG_SOC}>)
+
+# Generate PDL specific define (w. *_device) for SOC module (e.g: CYBLE_416045_02)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_CYBLE_416045_02 CYBLE_416045_02_device)
 
 # Add mtb-pdl-cat1
 zephyr_include_directories(${pdl_drv_dir}/include)
@@ -19,11 +24,12 @@ zephyr_library_sources(${pdl_dev_cat1a_dir}/source/cy_device.c)
 zephyr_library_sources(${pdl_drv_dir}/source/TOOLCHAIN_GCC_ARM/cy_syslib_ext.S)
 
 # Peripheral drivers
-zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6      ${pdl_drv_dir}/source/cy_sysint.c)
+zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6_LEGACY      ${pdl_drv_dir}/source/cy_sysint.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC      ${pdl_drv_dir}/source/cy_sar.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_I2C      ${pdl_drv_dir}/source/cy_scb_i2c.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_LPTIMER  ${pdl_drv_dir}/source/cy_mcwdt.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_PWM      ${pdl_drv_dir}/source/cy_tcpwm_pwm.c)
+zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_RTC      ${pdl_drv_dir}/source/cy_rtc.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SDIO     ${pdl_drv_dir}/source/cy_sd_host.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SPI      ${pdl_drv_dir}/source/cy_scb_spi.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_TIMER    ${pdl_drv_dir}/source/cy_tcpwm_counter.c)

soc/cypress/CMakeLists.txt

@@ -1,8 +0,0 @@
-#
-# Copyright (c) 2018, Cypress
-# Copyright (c) 2021, ATL Electronics
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-add_subdirectory(psoc6)

soc/cypress/Kconfig

@@ -1,9 +0,0 @@
-# Copyright (c) 2018, Cypress
-# Copyright (c) 2020, ATL Electronics
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1
-
-rsource "*/Kconfig"
-
-endif # SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1

soc/cypress/Kconfig.defconfig

@@ -1,8 +0,0 @@
-# Copyright (c) 2018, Cypress
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1
-
-rsource "*/Kconfig.defconfig"
-
-endif # SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1

soc/cypress/Kconfig.soc

@@ -1,17 +0,0 @@
-# Copyright (c) 2018, Cypress
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_FAMILY_PSOC6
-	bool
-
-config SOC_FAMILY_INFINEON_CAT1
-	bool
-
-config SOC_FAMILY_INFINEON_CAT1A
-	bool
-
-config SOC_FAMILY
-	default "psoc6" if SOC_FAMILY_PSOC6
-	default "infineon_cat1" if SOC_FAMILY_INFINEON_CAT1
-
-rsource "*/Kconfig.soc"

soc/cypress/psoc6/CMakeLists.txt

@@ -1,32 +0,0 @@
-#
-# Copyright (c) 2018, Cypress
-# Copyright (c) 2020, ATL Electronics
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-if(CONFIG_SOC_SERIES_PSOC62 OR CONFIG_SOC_SERIES_PSOC63)
-  add_subdirectory(old/common)
-  zephyr_include_directories(old)
-  zephyr_sources(old/soc.c)
-
-  zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 NOINIT old/noinit.ld)
-  zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 RWDATA old/rwdata.ld)
-else()
-  zephyr_include_directories(new)
-  zephyr_include_directories(new/common)
-  zephyr_sources(new/soc.c)
-
-  # Add sections
-  zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 NOINIT new/noinit.ld)
-
-  # Add section for cm0p image ROM
-  zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ROM_START SORT_KEY 0x0cm0p new/rom_cm0image.ld)
-
-  # Add section for cm0p image RAM
-  zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A RAM_SECTIONS SORT_KEY 0 new/ram_cm0image.ld)
-  zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A RAMFUNC_SECTION SORT_KEY 0 new/ram_func.ld)
-  zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 RODATA SORT_KEY 0 new/rom.ld)
-endif()
-
-set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/cypress/psoc6/Kconfig

@@ -1,58 +0,0 @@
-# Cypress Semiconductor PSoC6 series configuration options
-# Copyright (c) 2018, Cypress
-# Copyright (c) 2020, ATL Electronics
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_PSOC62_PSOC63
-	bool
-	select ARM
-	select HAS_CYPRESS_DRIVERS
-	select CPU_CORTEX_M0PLUS if SOC_CY8C6247_M0 || SOC_CY8C6347_M0
-	select CPU_CORTEX_M_HAS_SYSTICK if SOC_CY8C6247_M0 || SOC_CY8C6347_M0
-	select CPU_CORTEX_M_HAS_VTOR if SOC_CY8C6247_M0 || SOC_CY8C6347_M0
-	select CPU_HAS_ARM_MPU if SOC_CY8C6247_M0 || SOC_CY8C6347_M0
-	select CPU_CORTEX_M4 if SOC_CY8C6247_M4 || SOC_CY8C6347_M4
-	select CPU_CORTEX_M_HAS_DWT if SOC_CY8C6247_M4 || SOC_CY8C6347_M4
-	select CPU_CORTEX_M_HAS_SYSTICK if SOC_CY8C6247_M4 || SOC_CY8C6347_M4
-	select CPU_HAS_ARM_MPU if SOC_CY8C6247_M4 || SOC_CY8C6347_M4
-	select CPU_HAS_FPU if SOC_CY8C6247_M4 || SOC_CY8C6347_M4
-
-config SOC_SERIES_PSOC62
-	select SOC_SERIES_PSOC62_PSOC63
-
-config SOC_SERIES_PSOC63
-	select SOC_SERIES_PSOC62_PSOC63
-
-config SOC_PSOC6_M0_ENABLES_M4
-	bool "Dual-core support [activate Cortex-M4]"
-	depends on SOC_CY8C6247_M0 || SOC_CY8C6347_M0
-	help
-	  Cortex-M0 CPU should boot Cortex-M4
-
-config SOC_DIE_PSOC6
-	select ARM
-	select CPU_CORTEX_M4
-	select CPU_HAS_ARM_MPU
-	select DYNAMIC_INTERRUPTS
-	select CPU_HAS_FPU
-
-if SOC_FAMILY_INFINEON_CAT1A
-
-## PSoC™ 6 Cortex M0+ prebuilt images
-choice
-	prompt "PSoC™ 6 Cortex M0+ prebuilt images"
-	help
-	  Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSoC™ 6
-	  dual-core MCU. The image is responsible for booting the Cortex-M4 on the device.
-
-config SOC_PSOC6_CM0P_IMAGE_SLEEP
-	bool "DeepSleep"
-	help
-	  DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSoC™ 6 BLE
-	  dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4
-	  application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4
-	  linker script.
-
-endchoice
-
-endif # SOC_FAMILY_INFINEON_CAT1A

soc/cypress/psoc6/Kconfig.defconfig

@@ -1,30 +0,0 @@
-# Cypress Semiconductor PSoC6 series configuration options
-# Copyright (c) 2018, Cypress
-# Copyright (c) 2020, ATL Electronics
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_PSOC62 || SOC_SERIES_PSOC63
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 50000000
-
-rsource "old/Kconfig.defconfig.psoc*"
-
-endif # SOC_SERIES_PSOC62 || SOC_SERIES_PSOC63
-
-if SOC_FAMILY_INFINEON_CAT1
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 100000000
-
-config SOC_PSOC6_CM0P_IMAGE_ROM_SIZE
-	hex
-	default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP
-
-config SOC_PSOC6_CM0P_IMAGE_RAM_SIZE
-	hex
-	default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP
-
-rsource "new/Kconfig.defconfig.psoc6*"
-
-endif # SOC_FAMILY_INFINEON_CAT1

soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m0

@@ -1,10 +0,0 @@
-# Cypress PSoC6 CM0 platform configuration options
-# Copyright (c) 2018, Cypress
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_CY8C6247_M0 || SOC_CY8C6347_M0
-
-config NUM_IRQS
-	default 32
-
-endif # SOC_CY8C6247_M0 || SOC_CY8C6347_M0

soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m4

@@ -1,10 +0,0 @@
-# Cypress PSoC6 CM4 platform configuration options
-# Copyright (c) 2018, Cypress
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_CY8C6247_M4 || SOC_CY8C6347_M4
-
-config NUM_IRQS
-	default 147
-
-endif # SOC_CY8C6247_M4 || SOC_CY8C6347_M4

soc/cypress/psoc6/old/common/CMakeLists.txt

@@ -1,6 +0,0 @@
-# Copyright (c) 2021 ATL Electronics
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_include_directories(.)
-
-zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 soc_gpio.c)

soc/infineon/cat1a/CMakeLists.txt

@@ -0,0 +1,30 @@
+# Copyright (c) 2024 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_FAMILY_PSOC6)
+  zephyr_include_directories(common)
+  zephyr_sources(common/soc.c)
+
+  # Add sections
+  zephyr_linker_sources(NOINIT common/noinit.ld)
+
+  # Add section for cm0p image ROM
+  zephyr_linker_sources(ROM_START SORT_KEY 0x0cm0p common/rom_cm0image.ld)
+
+  # Add section for cm0p image RAM
+  zephyr_linker_sources(RAM_SECTIONS SORT_KEY 0 common/ram_cm0image.ld)
+  zephyr_linker_sources(RAMFUNC_SECTION SORT_KEY 0 common/ram_func.ld)
+  zephyr_linker_sources(RODATA SORT_KEY 0 common/rom.ld)
+
+endif()
+
+if(CONFIG_SOC_FAMILY_PSOC6_LEGACY)
+  zephyr_include_directories(psoc6_legacy)
+  zephyr_sources(psoc6_legacy/soc.c)
+  zephyr_sources(psoc6_legacy/soc_gpio.c)
+
+  zephyr_linker_sources(NOINIT psoc6_legacy/noinit.ld)
+  zephyr_linker_sources(RWDATA psoc6_legacy/rwdata.ld)
+endif()
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/infineon/cat1a/Kconfig

@@ -0,0 +1,62 @@
+# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Infineon CAT1A devices
+
+# Family definitions
+config SOC_FAMILY_PSOC6
+	select ARM
+	select CPU_CORTEX_M4
+	select CPU_HAS_ARM_MPU
+	select DYNAMIC_INTERRUPTS
+	select CPU_HAS_FPU
+	select SOC_FAMILY_INFINEON_CAT1
+
+config SOC_FAMILY_PSOC6_LEGACY
+	select ARM
+	select HAS_CYPRESS_DRIVERS
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_HAS_ARM_MPU
+
+config SOC_FAMILY_PSOC6_LEGACY_M4
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+
+config SOC_FAMILY_PSOC6_LEGACY_M0
+	select CPU_CORTEX_M0PLUS
+	select CPU_CORTEX_M_HAS_VTOR
+
+config SOC_PSOC6_M0_ENABLES_M4
+	bool "Dual-core support [activate Cortex-M4]"
+	depends on SOC_FAMILY_PSOC6_LEGACY_M0
+	help
+	  Cortex-M0 CPU should boot Cortex-M4
+
+if SOC_FAMILY_PSOC6
+## PSoC™ 6 Cortex M0+ prebuilt images
+choice
+	prompt "PSoC™ 6 Cortex M0+ prebuilt images"
+	help
+	  Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSoC™ 6
+	  dual-core MCU. The image is responsible for booting the Cortex-M4 on the device.
+
+config SOC_PSOC6_CM0P_IMAGE_SLEEP
+	bool "DeepSleep"
+	help
+	  DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSoC™ 6 BLE
+	  dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4
+	  application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4
+	  linker script.
+endchoice
+
+config SOC_PSOC6_CM0P_IMAGE_ROM_SIZE
+	hex
+	default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP
+
+config SOC_PSOC6_CM0P_IMAGE_RAM_SIZE
+	hex
+	default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP
+
+endif # SOC_FAMILY_PSOC6

soc/infineon/cat1a/Kconfig.defconfig

@@ -0,0 +1,10 @@
+# PSOC CAT1A Configuration
+
+# Copyright (c) 2024 Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_INFINEON_CAT1A
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_INFINEON_CAT1A

soc/infineon/cat1a/Kconfig.soc

@@ -0,0 +1,61 @@
+# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# MPNs definitions
+rsource "*/Kconfig.soc"
+
+# Infineon CAT1A devices
+
+# Category definitions
+config SOC_FAMILY_INFINEON_CAT1
+	bool
+
+config SOC_FAMILY_INFINEON_CAT1A
+	bool
+
+# Family definitions
+config SOC_FAMILY_PSOC6
+	bool
+
+config SOC_FAMILY_PSOC6_LEGACY
+	bool
+
+config SOC_FAMILY_PSOC6_LEGACY_M4
+	bool
+
+config SOC_FAMILY_PSOC6_LEGACY_M0
+	bool
+
+# Cypress PSoC™ 6 MCU lines
+config SOC_SERIES_PSOC6_60
+	bool
+	select SOC_FAMILY_PSOC6 if !SOC_FAMILY_PSOC6_LEGACY
+	select SOC_FAMILY_INFINEON_CAT1A
+
+config SOC_SERIES_PSOC6_61
+	bool
+	select SOC_FAMILY_PSOC6 if !SOC_FAMILY_PSOC6_LEGACY
+	select SOC_FAMILY_INFINEON_CAT1A
+
+config SOC_SERIES_PSOC6_62
+	bool
+	select SOC_FAMILY_PSOC6 if !SOC_FAMILY_PSOC6_LEGACY
+	select SOC_FAMILY_INFINEON_CAT1A
+
+config SOC_SERIES_PSOC6_63
+	bool
+	select SOC_FAMILY_PSOC6 if !SOC_FAMILY_PSOC6_LEGACY
+	select SOC_FAMILY_INFINEON_CAT1A
+
+config SOC_SERIES_PSOC6_64
+	bool
+	select SOC_FAMILY_PSOC6 if !SOC_FAMILY_PSOC6_LEGACY
+	select SOC_FAMILY_INFINEON_CAT1A
+
+config SOC_SERIES
+	default "psoc6_60" if SOC_SERIES_PSOC6_60
+	default "psoc6_61" if SOC_SERIES_PSOC6_61
+	default "psoc6_62" if SOC_SERIES_PSOC6_62
+	default "psoc6_63" if SOC_SERIES_PSOC6_63
+	default "psoc6_64" if SOC_SERIES_PSOC6_64

soc/infineon/cat1a/psoc6_01/Kconfig.defconfig

@@ -1,4 +1,4 @@
-# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
+# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
 # an affiliate of Cypress Semiconductor Corporation
 # SPDX-License-Identifier: Apache-2.0
 
@@ -10,6 +10,9 @@ config NUM_IRQS
 	default 32 if CPU_CORTEX_M0PLUS
 	default 147 if CPU_CORTEX_M4
 
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 100000000
+
 # add additional die specific params
 
 endif # SOC_DIE_PSOC6_01

soc/infineon/cat1a/psoc6_01/Kconfig.soc

@@ -0,0 +1,483 @@
+# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# SOC die
+config SOC_DIE_PSOC6_01
+	bool
+
+# SOC packages
+config SOC_PACKAGE_PSOC6_01_124_BGA
+	bool
+
+config SOC_PACKAGE_PSOC6_01_116_BGA_BLE
+	bool
+
+config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE
+	bool
+
+config SOC_PACKAGE_PSOC6_01_80_WLCSP
+	bool
+
+config SOC_PACKAGE_PSOC6_01_116_BGA_USB
+	bool
+
+config SOC_PACKAGE_PSOC6_01_124_BGA_SIP
+	bool
+
+config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB
+	bool
+
+config SOC_PACKAGE_PSOC6_01_68_QFN_BLE
+	bool
+
+# Infineon PSoC6_01 series MCUs
+config SOC_CY8C6036BZI_F04
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_60
+
+config SOC_CY8C6016BZI_F04
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_60
+
+config SOC_CY8C6116BZI_F54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6136BZI_F14
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6136BZI_F34
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6137BZI_F14
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6137BZI_F34
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6137BZI_F54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6117BZI_F34
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6246BZI_D04
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6247BZI_D44
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6247BZI_D34
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6247BZI_D54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6336BZI_BLF03
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6316BZI_BLF03
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6316BZI_BLF53
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6336BZI_BLD13
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347BZI_BLD43
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347BZI_BLD33
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347BZI_BLD53
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347FMI_BLD13
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347FMI_BLD43
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347FMI_BLD33
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347FMI_BLD53
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6137FDI_F02
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_80_WLCSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6117FDI_F02
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_80_WLCSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6247FDI_D02
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_80_WLCSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6247FDI_D32
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_80_WLCSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6336BZI_BUD13
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_USB
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347BZI_BUD43
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_USB
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347BZI_BUD33
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_USB
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347BZI_BUD53
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_USB
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6337BZI_BLF13
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6136FDI_F42
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_80_WLCSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6247FDI_D52
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_80_WLCSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6136FTI_F42
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_80_WLCSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6247FTI_D52
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_80_WLCSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6247BZI_AUD54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6336BZI_BLF04
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA_SIP
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6316BZI_BLF04
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA_SIP
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6316BZI_BLF54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA_SIP
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6336BZI_BLD14
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA_SIP
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347BZI_BLD44
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA_SIP
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347BZI_BLD34
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA_SIP
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347BZI_BLD54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA_SIP
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6247BFI_D54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6347FMI_BUD53
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347FMI_BUD13
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347FMI_BUD43
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347FMI_BUD33
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6137WI_F54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6117WI_F34
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6247WI_D54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6336LQI_BLF02
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_68_QFN_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6336LQI_BLF42
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_68_QFN_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6347LQI_BLD52
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_68_QFN_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC_CY8C6247BTI_D54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6246BTI_D54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6147BTI_F54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6146BTI_F54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CYB06447BZI_BLD54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA_SIP
+	select SOC_SERIES_PSOC6_64
+
+config SOC_CYB06447BZI_BLD53
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_BLE
+	select SOC_SERIES_PSOC6_64
+
+config SOC_CYB06447BZI_D54
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_124_BGA
+	select SOC_SERIES_PSOC6_64
+
+config SOC_CYBLE_416045_02
+	bool
+	select SOC_DIE_PSOC6_01
+	select SOC_PACKAGE_PSOC6_01_116_BGA_BLE
+	select SOC_SERIES_PSOC6_63
+
+config SOC
+	default "cy8c6036bzi_f04" if SOC_CY8C6036BZI_F04
+	default "cy8c6016bzi_f04" if SOC_CY8C6016BZI_F04
+	default "cy8c6116bzi_f54" if SOC_CY8C6116BZI_F54
+	default "cy8c6136bzi_f14" if SOC_CY8C6136BZI_F14
+	default "cy8c6136bzi_f34" if SOC_CY8C6136BZI_F34
+	default "cy8c6137bzi_f14" if SOC_CY8C6137BZI_F14
+	default "cy8c6137bzi_f34" if SOC_CY8C6137BZI_F34
+	default "cy8c6137bzi_f54" if SOC_CY8C6137BZI_F54
+	default "cy8c6117bzi_f34" if SOC_CY8C6117BZI_F34
+	default "cy8c6246bzi_d04" if SOC_CY8C6246BZI_D04
+	default "cy8c6247bzi_d44" if SOC_CY8C6247BZI_D44
+	default "cy8c6247bzi_d34" if SOC_CY8C6247BZI_D34
+	default "cy8c6247bzi_d54" if SOC_CY8C6247BZI_D54
+	default "cy8c6336bzi_blf03" if SOC_CY8C6336BZI_BLF03
+	default "cy8c6316bzi_blf03" if SOC_CY8C6316BZI_BLF03
+	default "cy8c6316bzi_blf53" if SOC_CY8C6316BZI_BLF53
+	default "cy8c6336bzi_bld13" if SOC_CY8C6336BZI_BLD13
+	default "cy8c6347bzi_bld43" if SOC_CY8C6347BZI_BLD43
+	default "cy8c6347bzi_bld33" if SOC_CY8C6347BZI_BLD33
+	default "cy8c6347bzi_bld53" if SOC_CY8C6347BZI_BLD53
+	default "cy8c6347fmi_bld13" if SOC_CY8C6347FMI_BLD13
+	default "cy8c6347fmi_bld43" if SOC_CY8C6347FMI_BLD43
+	default "cy8c6347fmi_bld33" if SOC_CY8C6347FMI_BLD33
+	default "cy8c6347fmi_bld53" if SOC_CY8C6347FMI_BLD53
+	default "cy8c6137fdi_f02" if SOC_CY8C6137FDI_F02
+	default "cy8c6117fdi_f02" if SOC_CY8C6117FDI_F02
+	default "cy8c6247fdi_d02" if SOC_CY8C6247FDI_D02
+	default "cy8c6247fdi_d32" if SOC_CY8C6247FDI_D32
+	default "cy8c6336bzi_bud13" if SOC_CY8C6336BZI_BUD13
+	default "cy8c6347bzi_bud43" if SOC_CY8C6347BZI_BUD43
+	default "cy8c6347bzi_bud33" if SOC_CY8C6347BZI_BUD33
+	default "cy8c6347bzi_bud53" if SOC_CY8C6347BZI_BUD53
+	default "cy8c6337bzi_blf13" if SOC_CY8C6337BZI_BLF13
+	default "cy8c6136fdi_f42" if SOC_CY8C6136FDI_F42
+	default "cy8c6247fdi_d52" if SOC_CY8C6247FDI_D52
+	default "cy8c6136fti_f42" if SOC_CY8C6136FTI_F42
+	default "cy8c6247fti_d52" if SOC_CY8C6247FTI_D52
+	default "cy8c6247bzi_aud54" if SOC_CY8C6247BZI_AUD54
+	default "cy8c6336bzi_blf04" if SOC_CY8C6336BZI_BLF04
+	default "cy8c6316bzi_blf04" if SOC_CY8C6316BZI_BLF04
+	default "cy8c6316bzi_blf54" if SOC_CY8C6316BZI_BLF54
+	default "cy8c6336bzi_bld14" if SOC_CY8C6336BZI_BLD14
+	default "cy8c6347bzi_bld44" if SOC_CY8C6347BZI_BLD44
+	default "cy8c6347bzi_bld34" if SOC_CY8C6347BZI_BLD34
+	default "cy8c6347bzi_bld54" if SOC_CY8C6347BZI_BLD54
+	default "cy8c6247bfi_d54" if SOC_CY8C6247BFI_D54
+	default "cy8c6347fmi_bud53" if SOC_CY8C6347FMI_BUD53
+	default "cy8c6347fmi_bud13" if SOC_CY8C6347FMI_BUD13
+	default "cy8c6347fmi_bud43" if SOC_CY8C6347FMI_BUD43
+	default "cy8c6347fmi_bud33" if SOC_CY8C6347FMI_BUD33
+	default "cy8c6137wi_f54" if SOC_CY8C6137WI_F54
+	default "cy8c6117wi_f34" if SOC_CY8C6117WI_F34
+	default "cy8c6247wi_d54" if SOC_CY8C6247WI_D54
+	default "cy8c6336lqi_blf02" if SOC_CY8C6336LQI_BLF02
+	default "cy8c6336lqi_blf42" if SOC_CY8C6336LQI_BLF42
+	default "cy8c6347lqi_bld52" if SOC_CY8C6347LQI_BLD52
+	default "cy8c6247bti_d54" if SOC_CY8C6247BTI_D54
+	default "cy8c6246bti_d54" if SOC_CY8C6246BTI_D54
+	default "cy8c6147bti_f54" if SOC_CY8C6147BTI_F54
+	default "cy8c6146bti_f54" if SOC_CY8C6146BTI_F54
+	default "cyb06447bzi_bld54" if SOC_CYB06447BZI_BLD54
+	default "cyb06447bzi_bld53" if SOC_CYB06447BZI_BLD53
+	default "cyb06447bzi_d54" if SOC_CYB06447BZI_D54
+	default "cyble_416045_02" if SOC_CYBLE_416045_02

soc/infineon/cat1a/psoc6_02/Kconfig.defconfig

@@ -1,4 +1,4 @@
-# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
+# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
 # an affiliate of Cypress Semiconductor Corporation
 # SPDX-License-Identifier: Apache-2.0
 
@@ -7,9 +7,12 @@
 if SOC_DIE_PSOC6_02
 
 config NUM_IRQS
-	default 32 if CPU_CORTEX_M0PLUS
+	default 16 if CPU_CORTEX_M0PLUS
 	default 168 if CPU_CORTEX_M4
 
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 100000000
+
 # add additional die specific params
 
 endif # SOC_DIE_PSOC6_02

soc/infineon/cat1a/psoc6_02/Kconfig.soc

@@ -0,0 +1,254 @@
+# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# SOC die
+config SOC_DIE_PSOC6_02
+	bool
+
+# SOC packages
+config SOC_PACKAGE_PSOC6_02_124_BGA
+	bool
+
+config SOC_PACKAGE_PSOC6_02_100_WLCSP
+	bool
+
+config SOC_PACKAGE_PSOC6_02_128_TQFP
+	bool
+
+config SOC_PACKAGE_PSOC6_02_68_QFN
+	bool
+
+# Infineon PSoC6_02 series MCUs
+config SOC_CYB0644ABZI_S2D44
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_124_BGA
+	select SOC_SERIES_PSOC6_64
+
+config SOC_CYS0644ABZI_S2D44
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_124_BGA
+	select SOC_SERIES_PSOC6_64
+
+config SOC_CYS0644AFNI_S2D43
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_100_WLCSP
+	select SOC_SERIES_PSOC6_64
+
+config SOC_CY8C624ABZI_S2D44A0
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C624ABZI_S2D44
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C624AAZI_S2D44
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_128_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C624AFNI_S2D43
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_100_WLCSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C624ABZI_S2D04
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C624ABZI_S2D14
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C624AAZI_S2D14
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_128_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6248AZI_S2D14
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_128_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6248BZI_S2D44
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6248AZI_S2D44
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_128_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6248FNI_S2D43
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_100_WLCSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C614ABZI_S2F04
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C614AAZI_S2F04
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_128_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C614AFNI_S2F03
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_100_WLCSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C614AAZI_S2F14
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_128_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C614ABZI_S2F44
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C614AAZI_S2F44
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_128_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C614AFNI_S2F43
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_100_WLCSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6148BZI_S2F44
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_124_BGA
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6148AZI_S2F44
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_128_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6148FNI_S2F43
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_100_WLCSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C624ABZI_D44
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_124_BGA
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C624ALQI_S2D42
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C624ALQI_S2D02
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6248LQI_S2D42
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6248LQI_S2D02
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C614ALQI_S2F42
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C614ALQI_S2F02
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6148LQI_S2F42
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6148LQI_S2F02
+	bool
+	select SOC_DIE_PSOC6_02
+	select SOC_PACKAGE_PSOC6_02_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC
+	default "cyb0644abzi_s2d44" if SOC_CYB0644ABZI_S2D44
+	default "cys0644abzi_s2d44" if SOC_CYS0644ABZI_S2D44
+	default "cys0644afni_s2d43" if SOC_CYS0644AFNI_S2D43
+	default "cy8c624abzi_s2d44a0" if SOC_CY8C624ABZI_S2D44A0
+	default "cy8c624abzi_s2d44" if SOC_CY8C624ABZI_S2D44
+	default "cy8c624aazi_s2d44" if SOC_CY8C624AAZI_S2D44
+	default "cy8c624afni_s2d43" if SOC_CY8C624AFNI_S2D43
+	default "cy8c624abzi_s2d04" if SOC_CY8C624ABZI_S2D04
+	default "cy8c624abzi_s2d14" if SOC_CY8C624ABZI_S2D14
+	default "cy8c624aazi_s2d14" if SOC_CY8C624AAZI_S2D14
+	default "cy8c6248azi_s2d14" if SOC_CY8C6248AZI_S2D14
+	default "cy8c6248bzi_s2d44" if SOC_CY8C6248BZI_S2D44
+	default "cy8c6248azi_s2d44" if SOC_CY8C6248AZI_S2D44
+	default "cy8c6248fni_s2d43" if SOC_CY8C6248FNI_S2D43
+	default "cy8c614abzi_s2f04" if SOC_CY8C614ABZI_S2F04
+	default "cy8c614aazi_s2f04" if SOC_CY8C614AAZI_S2F04
+	default "cy8c614afni_s2f03" if SOC_CY8C614AFNI_S2F03
+	default "cy8c614aazi_s2f14" if SOC_CY8C614AAZI_S2F14
+	default "cy8c614abzi_s2f44" if SOC_CY8C614ABZI_S2F44
+	default "cy8c614aazi_s2f44" if SOC_CY8C614AAZI_S2F44
+	default "cy8c614afni_s2f43" if SOC_CY8C614AFNI_S2F43
+	default "cy8c6148bzi_s2f44" if SOC_CY8C6148BZI_S2F44
+	default "cy8c6148azi_s2f44" if SOC_CY8C6148AZI_S2F44
+	default "cy8c6148fni_s2f43" if SOC_CY8C6148FNI_S2F43
+	default "cy8c624abzi_d44" if SOC_CY8C624ABZI_D44
+	default "cy8c624alqi_s2d42" if SOC_CY8C624ALQI_S2D42
+	default "cy8c624alqi_s2d02" if SOC_CY8C624ALQI_S2D02
+	default "cy8c6248lqi_s2d42" if SOC_CY8C6248LQI_S2D42
+	default "cy8c6248lqi_s2d02" if SOC_CY8C6248LQI_S2D02
+	default "cy8c614alqi_s2f42" if SOC_CY8C614ALQI_S2F42
+	default "cy8c614alqi_s2f02" if SOC_CY8C614ALQI_S2F02
+	default "cy8c6148lqi_s2f42" if SOC_CY8C6148LQI_S2F42
+	default "cy8c6148lqi_s2f02" if SOC_CY8C6148LQI_S2F02

soc/infineon/cat1a/psoc6_03/Kconfig.defconfig

@@ -0,0 +1,18 @@
+# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Infineon PSoC6_03 based MCU default configuration
+
+if SOC_DIE_PSOC6_03
+
+config NUM_IRQS
+	default 16 if CPU_CORTEX_M0PLUS
+	default 174 if CPU_CORTEX_M4
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 100000000
+
+# add additional die specific params
+
+endif # SOC_DIE_PSOC6_03

soc/infineon/cat1a/psoc6_03/Kconfig.soc

@@ -0,0 +1,209 @@
+# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# SOC die
+config SOC_DIE_PSOC6_03
+	bool
+
+# SOC packages
+config SOC_PACKAGE_PSOC6_03_100_TQFP
+	bool
+
+config SOC_PACKAGE_PSOC6_03_68_QFN
+	bool
+
+config SOC_PACKAGE_PSOC6_03_49_WLCSP
+	bool
+
+# Infineon PSoC6_03 series MCUs
+config SOC_CY8C6245AZI_S3D72
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_100_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6245LQI_S3D72
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6245FNI_S3D71
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_49_WLCSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6245AZI_S3D62
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_100_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6245LQI_S3D62
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6245AZI_S3D42
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_100_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6245LQI_S3D42
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CYB06445LQI_S3D42
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_68_QFN
+	select SOC_SERIES_PSOC6_64
+
+config SOC_CY8C6245FNI_S3D41
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_49_WLCSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6245AZI_S3D12
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_100_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6245LQI_S3D12
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6245FNI_S3D11
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_49_WLCSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6245AZI_S3D02
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_100_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6245LQI_S3D02
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6145AZI_S3F72
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_100_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6145LQI_S3F72
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6145FNI_S3F71
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_49_WLCSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6145AZI_S3F62
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_100_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6145LQI_S3F62
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6145AZI_S3F42
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_100_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6145LQI_S3F42
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6145FNI_S3F41
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_49_WLCSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6145AZI_S3F12
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_100_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6145LQI_S3F12
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6145FNI_S3F11
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_49_WLCSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6145AZI_S3F02
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_100_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6145LQI_S3F02
+	bool
+	select SOC_DIE_PSOC6_03
+	select SOC_PACKAGE_PSOC6_03_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC
+	default "cy8c6245azi_s3d72" if SOC_CY8C6245AZI_S3D72
+	default "cy8c6245lqi_s3d72" if SOC_CY8C6245LQI_S3D72
+	default "cy8c6245fni_s3d71" if SOC_CY8C6245FNI_S3D71
+	default "cy8c6245azi_s3d62" if SOC_CY8C6245AZI_S3D62
+	default "cy8c6245lqi_s3d62" if SOC_CY8C6245LQI_S3D62
+	default "cy8c6245azi_s3d42" if SOC_CY8C6245AZI_S3D42
+	default "cy8c6245lqi_s3d42" if SOC_CY8C6245LQI_S3D42
+	default "cyb06445lqi_s3d42" if SOC_CYB06445LQI_S3D42
+	default "cy8c6245fni_s3d41" if SOC_CY8C6245FNI_S3D41
+	default "cy8c6245azi_s3d12" if SOC_CY8C6245AZI_S3D12
+	default "cy8c6245lqi_s3d12" if SOC_CY8C6245LQI_S3D12
+	default "cy8c6245fni_s3d11" if SOC_CY8C6245FNI_S3D11
+	default "cy8c6245azi_s3d02" if SOC_CY8C6245AZI_S3D02
+	default "cy8c6245lqi_s3d02" if SOC_CY8C6245LQI_S3D02
+	default "cy8c6145azi_s3f72" if SOC_CY8C6145AZI_S3F72
+	default "cy8c6145lqi_s3f72" if SOC_CY8C6145LQI_S3F72
+	default "cy8c6145fni_s3f71" if SOC_CY8C6145FNI_S3F71
+	default "cy8c6145azi_s3f62" if SOC_CY8C6145AZI_S3F62
+	default "cy8c6145lqi_s3f62" if SOC_CY8C6145LQI_S3F62
+	default "cy8c6145azi_s3f42" if SOC_CY8C6145AZI_S3F42
+	default "cy8c6145lqi_s3f42" if SOC_CY8C6145LQI_S3F42
+	default "cy8c6145fni_s3f41" if SOC_CY8C6145FNI_S3F41
+	default "cy8c6145azi_s3f12" if SOC_CY8C6145AZI_S3F12
+	default "cy8c6145lqi_s3f12" if SOC_CY8C6145LQI_S3F12
+	default "cy8c6145fni_s3f11" if SOC_CY8C6145FNI_S3F11
+	default "cy8c6145azi_s3f02" if SOC_CY8C6145AZI_S3F02
+	default "cy8c6145lqi_s3f02" if SOC_CY8C6145LQI_S3F02

soc/infineon/cat1a/psoc6_04/Kconfig.defconfig

@@ -1,6 +1,5 @@
-# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
+# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
 # an affiliate of Cypress Semiconductor Corporation
-# Copyright (c) David Ullmann
 # SPDX-License-Identifier: Apache-2.0
 
 # Infineon PSoC6_04 based MCU default configuration
@@ -11,4 +10,9 @@ config NUM_IRQS
 	default 16 if CPU_CORTEX_M0PLUS
 	default 175 if CPU_CORTEX_M4
 
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 100000000
+
+# add additional die specific params
+
 endif # SOC_DIE_PSOC6_04

soc/infineon/cat1a/psoc6_04/Kconfig.soc

@@ -0,0 +1,275 @@
+# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# SOC die
+config SOC_DIE_PSOC6_04
+	bool
+
+# SOC packages
+config SOC_PACKAGE_PSOC6_04_64_TQFP
+	bool
+
+config SOC_PACKAGE_PSOC6_04_68_QFN
+	bool
+
+config SOC_PACKAGE_PSOC6_04_80_TQFP
+	bool
+
+config SOC_PACKAGE_PSOC6_04_80_M_CSP
+	bool
+
+# Infineon PSoC6_04 series MCUs
+config SOC_CY8C6244AZI_S4D92
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244LQI_S4D92
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244AZI_S4D93
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244AZI_S4D82
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244LQI_S4D82
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244AZI_S4D83
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244AZI_S4D62
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244LQI_S4D62
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244AZI_S4D12
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244LQI_S4D12
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6144AZI_S4F92
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144LQI_S4F92
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144AZI_S4F93
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144AZI_S4F82
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144LQI_S4F82
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144AZI_S4F83
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144AZI_S4F62
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144LQI_S4F62
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144AZI_S4F12
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144LQI_S4F12
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6244AZQ_S4D92
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244LQQ_S4D92
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244AZQ_S4D93
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_TQFP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6144AZQ_S4F92
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_64_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144LQQ_S4F92
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_68_QFN
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144AZQ_S4F93
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_TQFP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6244FMI_S4D93
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_M_CSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244FMI_S4D73
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_M_CSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244FMI_S4D53
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_M_CSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244FMI_S4D03
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_M_CSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6244FMQ_S4D93
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_M_CSP
+	select SOC_SERIES_PSOC6_62
+
+config SOC_CY8C6144FMI_S4F93
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_M_CSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144FMI_S4F73
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_M_CSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144FMI_S4F53
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_M_CSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144FMI_S4F03
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_M_CSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC_CY8C6144FMQ_S4F93
+	bool
+	select SOC_DIE_PSOC6_04
+	select SOC_PACKAGE_PSOC6_04_80_M_CSP
+	select SOC_SERIES_PSOC6_61
+
+config SOC
+	default "cy8c6244azi_s4d92" if SOC_CY8C6244AZI_S4D92
+	default "cy8c6244lqi_s4d92" if SOC_CY8C6244LQI_S4D92
+	default "cy8c6244azi_s4d93" if SOC_CY8C6244AZI_S4D93
+	default "cy8c6244azi_s4d82" if SOC_CY8C6244AZI_S4D82
+	default "cy8c6244lqi_s4d82" if SOC_CY8C6244LQI_S4D82
+	default "cy8c6244azi_s4d83" if SOC_CY8C6244AZI_S4D83
+	default "cy8c6244azi_s4d62" if SOC_CY8C6244AZI_S4D62
+	default "cy8c6244lqi_s4d62" if SOC_CY8C6244LQI_S4D62
+	default "cy8c6244azi_s4d12" if SOC_CY8C6244AZI_S4D12
+	default "cy8c6244lqi_s4d12" if SOC_CY8C6244LQI_S4D12
+	default "cy8c6144azi_s4f92" if SOC_CY8C6144AZI_S4F92
+	default "cy8c6144lqi_s4f92" if SOC_CY8C6144LQI_S4F92
+	default "cy8c6144azi_s4f93" if SOC_CY8C6144AZI_S4F93
+	default "cy8c6144azi_s4f82" if SOC_CY8C6144AZI_S4F82
+	default "cy8c6144lqi_s4f82" if SOC_CY8C6144LQI_S4F82
+	default "cy8c6144azi_s4f83" if SOC_CY8C6144AZI_S4F83
+	default "cy8c6144azi_s4f62" if SOC_CY8C6144AZI_S4F62
+	default "cy8c6144lqi_s4f62" if SOC_CY8C6144LQI_S4F62
+	default "cy8c6144azi_s4f12" if SOC_CY8C6144AZI_S4F12
+	default "cy8c6144lqi_s4f12" if SOC_CY8C6144LQI_S4F12
+	default "cy8c6244azq_s4d92" if SOC_CY8C6244AZQ_S4D92
+	default "cy8c6244lqq_s4d92" if SOC_CY8C6244LQQ_S4D92
+	default "cy8c6244azq_s4d93" if SOC_CY8C6244AZQ_S4D93
+	default "cy8c6144azq_s4f92" if SOC_CY8C6144AZQ_S4F92
+	default "cy8c6144lqq_s4f92" if SOC_CY8C6144LQQ_S4F92
+	default "cy8c6144azq_s4f93" if SOC_CY8C6144AZQ_S4F93
+	default "cy8c6244fmi_s4d93" if SOC_CY8C6244FMI_S4D93
+	default "cy8c6244fmi_s4d73" if SOC_CY8C6244FMI_S4D73
+	default "cy8c6244fmi_s4d53" if SOC_CY8C6244FMI_S4D53
+	default "cy8c6244fmi_s4d03" if SOC_CY8C6244FMI_S4D03
+	default "cy8c6244fmq_s4d93" if SOC_CY8C6244FMQ_S4D93
+	default "cy8c6144fmi_s4f93" if SOC_CY8C6144FMI_S4F93
+	default "cy8c6144fmi_s4f73" if SOC_CY8C6144FMI_S4F73
+	default "cy8c6144fmi_s4f53" if SOC_CY8C6144FMI_S4F53
+	default "cy8c6144fmi_s4f03" if SOC_CY8C6144FMI_S4F03
+	default "cy8c6144fmq_s4f93" if SOC_CY8C6144FMQ_S4F93

soc/infineon/cat1a/psoc6_legacy/Kconfig.defconfig

@@ -0,0 +1,18 @@
+# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Infineon PSoC6 (Legacy) based MCU default configuration
+
+if SOC_FAMILY_PSOC6_LEGACY
+
+config NUM_IRQS
+	default 32 if CPU_CORTEX_M0PLUS
+	default 147 if CPU_CORTEX_M4
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 50000000
+
+# add additional die specific params
+
+endif # SOC_FAMILY_PSOC6_LEGACY

soc/infineon/cat1a/psoc6_legacy/Kconfig.soc

@@ -0,0 +1,42 @@
+# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Infineon PSoC6 (legacy) series MCUs
+config SOC_CY8C6247_M0
+	bool
+	select SOC_SERIES_PSOC6_62
+	select SOC_FAMILY_PSOC6_LEGACY
+	select SOC_FAMILY_PSOC6_LEGACY_M0
+
+config SOC_CY8C6247_M4
+	bool
+	select SOC_SERIES_PSOC6_62
+	select SOC_FAMILY_PSOC6_LEGACY
+	select SOC_FAMILY_PSOC6_LEGACY_M4
+
+config SOC_CY8C6347_M0
+	bool
+	select SOC_SERIES_PSOC6_63
+	select SOC_FAMILY_PSOC6_LEGACY
+	select SOC_FAMILY_PSOC6_LEGACY_M0
+
+config SOC_CY8C6347_M4
+	bool
+	select SOC_SERIES_PSOC6_63
+	select SOC_FAMILY_PSOC6_LEGACY
+	select SOC_FAMILY_PSOC6_LEGACY_M4
+
+config SOC_PART_NUMBER_CY8C6247BZI_D54
+	bool
+
+config SOC_PART_NUMBER_CY8C6347BZI_BLD53
+	bool
+
+config SOC
+	default "cy8c6247" if SOC_CY8C6247_M0 || SOC_CY8C6247_M4
+	default "cy8c6347" if SOC_CY8C6347_M0 || SOC_CY8C6347_M4
+
+config SOC_PART_NUMBER
+	default "CY8C6247BZI_D54" if SOC_PART_NUMBER_CY8C6247BZI_D54
+	default "CY8C6347BZI_BLD53" if SOC_PART_NUMBER_CY8C6347BZI_BLD53

soc/infineon/cat1a/psoc6_legacy/soc.h

@@ -20,8 +20,8 @@
 #ifndef _ASMLANGUAGE
 
 #include <cy_device_headers.h>
-#include "../common/soc_gpio.h"
+#include "soc_gpio.h"
-#include "../common/cypress_psoc6_dt.h"
+#include "cypress_psoc6_dt.h"
 
 #endif /* !_ASMLANGUAGE */
 

soc/infineon/cat1a/soc.yml

@@ -1,19 +1,5 @@
 family:
-- name: psoc6
+- name: cat1a
-  series:
-  - name: psoc62
-    socs:
-    - name: cy8c6247
-      cpuclusters:
-      - name: m0
-      - name: m4
-  - name: psoc63
-    socs:
-    - name: cy8c6347
-      cpuclusters:
-      - name: m0
-      - name: m4
-- name: infineon_cat1
   series:
   - name: psoc6
     socs:
@@ -63,7 +49,6 @@ family:
     - name: cy8c6347bzi_bld34
     - name: cy8c6347bzi_bld54
     - name: cy8c6247bfi_d54
-    - name: cyble_416045_02
     - name: cy8c6347fmi_bud53
     - name: cy8c6347fmi_bud13
     - name: cy8c6347fmi_bud43
@@ -129,3 +114,12 @@ family:
     - name: cy8c6144lqi_s4f62
     - name: cy8c6144azi_s4f12
     - name: cy8c6144lqi_s4f12
+    - name: cyble_416045_02
+    - name: cy8c6247
+      cpuclusters:
+      - name: m0
+      - name: m4
+    - name: cy8c6347
+      cpuclusters:
+      - name: m0
+      - name: m4

soc/infineon/cat3/CMakeLists.txt

@@ -4,3 +4,5 @@
 # Author: Parthiban Nallathambi <parthiban@linumiz.com>
 
 add_subdirectory(${SOC_SERIES})
+
+zephyr_compile_definitions($<UPPER_CASE:${CONFIG_SOC}>_${CONFIG_SOC_PART_NUMBER})