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soc: ti_k3: Add TI J722s SoC MCU R5

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Add initial SoC support for the TI J722s SoC series MCU-domain
Cortex-R5 core.

TRM for J722s: https://www.ti.com/lit/zip/sprujb3

Signed-off-by: Andrew Davis <afd@ti.com>
This commit is contained in:
Andrew Davis 2024-10-23 13:39:23 -05:00 committed by Benjamin Cabé
parent 0fd3a992bd
commit 87a5410584
5 changed files with 102 additions and 1 deletions
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1
dts/arm/ti/j722s_main_r5.dtsi
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@ -10,6 +10,7 @@
#include <arm/armv7-r.dtsi>
#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
#include "j722s_mcu.dtsi"
#include "j722s_main.dtsi"
/ {

34
dts/arm/ti/j722s_mcu.dtsi Normal file
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@ -0,0 +1,34 @@
/*
* Copyright (c) 2024 Texas Instruments Incorporated
* Andrew Davis <afd@ti.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <freq.h>
#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
mcu_gpio0: gpio@4201010 {
compatible = "ti,davinci-gpio";
reg = <0x4201010 0x100>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
status = "disabled";
};
mcu_uart0: uart@4a00000 {
compatible = "ns16550";
reg = <0x04a00000 0x100>;
clock-frequency = <48000000>;
interrupts = <0 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-parent = <&vim>;
reg-shift = <2>;
status = "disabled";
};
};

61
dts/arm/ti/j722s_mcu_r5.dtsi Normal file
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@ -0,0 +1,61 @@
/*
* Copyright (c) 2024 Texas Instruments Incorporated
* Andrew Davis <afd@ti.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <freq.h>
#include <arm/armv7-r.dtsi>
#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
#include "j722s_mcu.dtsi"
#include "j722s_main.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-r5";
reg = <0>;
};
};
atcm: memory@0 {
device_type = "memory";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x00000000 DT_SIZE_K(32)>;
zephyr,memory-region = "ATCM";
};
btcm: memory@41010000 {
device_type = "memory";
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x41010000 DT_SIZE_K(32)>;
zephyr,memory-region = "BTCM";
};
vim: interrupt-controller@7ff0000 {
#address-cells = <1>;
compatible = "ti,vim";
reg = <0x07ff0000 0x2800>;
interrupt-controller;
#interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */
status = "okay";
};
systick_timer: timer@4800000 {
compatible = "ti,am654-timer";
reg = <0x04800000 0x70>;
interrupts = <0 28 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-parent = <&vim>;
status = "disabled";
};
};

6
soc/ti/k3/am6x/Kconfig.soc
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@ -43,6 +43,10 @@ config SOC_J722S_MAIN_R5F0_0
bool
select SOC_SERIES_AM6X_R5
config SOC_J722S_MCU_R5F0_0
bool
select SOC_SERIES_AM6X_R5
config SOC_SERIES
default "am6x" if SOC_SERIES_AM6X
@ -50,4 +54,4 @@ config SOC
default "am6234" if SOC_AM6234_M4 || SOC_AM6234_A53
default "am6442" if SOC_AM6442_M4
default "j721e" if SOC_J721E_MAIN_R5F0_0
default "j722s" if SOC_J722S_MAIN_R5F0_0
default "j722s" if SOC_J722S_MAIN_R5F0_0 || SOC_J722S_MCU_R5F0_0

1
soc/ti/k3/soc.yml
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@ -16,3 +16,4 @@ family:
- name: j722s
cpuclusters:
- name: main_r5f0_0
- name: mcu_r5f0_0