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riscv: irq: Adjust initialization of mtvec in non-legacy CLIC

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If CONFIG_LEGACY_CLIC is disabled, i.e. we adhere to the current CLIC
spec, the mode bits of mtvec have to be 0x3. Everything else is
reserved. Therefore if CONFIG_RISCV_VECTORED_MODE is enabled, the
current implementation is correct. If CONFIG_RISCV_VECTORED_MODE is
disabled, the mode bits have to be set, too.

Signed-off-by: Greter Raffael <rgreter@baumer.com>
This commit is contained in:
Greter Raffael 2023-12-21 15:15:19 +00:00 committed by Carles Cufí
parent ef5c28cab2
commit 899ee686d8
1 changed files with 10 additions and 0 deletions
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10
soc/riscv/common/riscv-privileged/vector.S
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@ -76,6 +76,14 @@ SECTION_FUNC(vectors, __start)
#else /* !CONFIG_RISCV_VECTORED_MODE */
#if defined(CONFIG_RISCV_HAS_CLIC) && !defined(CONFIG_LEGACY_CLIC)
la t0, _isr_wrapper
addi t0, t0, 0x03 /* Set mode bits to 3, signifying CLIC. Everything else is reserved. */
csrw mtvec, t0
#else /* !CONFIG_RISCV_HAS_CLIC || CONFIG_LEGACY_CLIC */
/*
* CLINT direct mode
*
@ -85,6 +93,8 @@ SECTION_FUNC(vectors, __start)
la t0, _isr_wrapper
csrw mtvec, t0
#endif /* CONFIG_RISCV_HAS_CLIC&& !CONFIG_LEGACY_CLIC */
#endif /* CONFIG_RISCV_VECTORED_MODE */
/* Jump to __reset */