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dts: riscv: sifive: fu740: add more cpus

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Update devicetree to support more cpus.

Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
This commit is contained in:
Franciszek Zdobylak 2023-03-29 07:36:21 +02:00 committed by Carles Cufí
parent ffe94b512f
commit 8a9be6eb0d
1 changed files with 53 additions and 1 deletions
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54
dts/riscv/sifive/riscv64-fu740.dtsi
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@ -31,7 +31,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cpu: cpu@0 { cpu0: cpu@0 {
compatible = "sifive,s7"; compatible = "sifive,s7";
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
@ -45,6 +45,58 @@
interrupt-controller; interrupt-controller;
}; };
}; };
cpu1: cpu@1 {
compatible = "sifive,u74";
device_type = "cpu";
mmu-type = "riscv,sv39";
reg = <0x1>;
riscv,isa = "rv64imafdc";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu2: cpu@2 {
compatible = "sifive,u74";
device_type = "cpu";
mmu-type = "riscv,sv39";
reg = <0x2>;
riscv,isa = "rv64imafdc";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu3: cpu@3 {
compatible = "sifive,u74";
device_type = "cpu";
mmu-type = "riscv,sv39";
reg = <0x3>;
riscv,isa = "rv64imafdc";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu4: cpu@4 {
compatible = "sifive,u74";
device_type = "cpu";
mmu-type = "riscv,sv39";
reg = <0x4>;
riscv,isa = "rv64imafdc";
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
}; };
soc { soc {