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drivers: gpio: Update gpio driver for Renesas RA series

Browse source 
Background of this modification is to make gpio driver code
provided by Renesas vendor to be an official support for Renesas
MCU on Zephyr

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
This commit is contained in:
Duy Phuong Hoang. Nguyen 2024-07-18 15:40:33 +07:00 committed by Anas Nashif
parent ffad404a6a
commit 922ee61b8d
9 changed files with 85 additions and 86 deletions
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2
drivers/gpio/CMakeLists.txt
View file

@ -66,7 +66,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_PCA95XX gpio_pca95xx.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_PCAL64XXA gpio_pcal64xxa.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_PCF857X gpio_pcf857x.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_PSOC6 gpio_psoc6.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_RA8 gpio_renesas_ra8.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_RA_IOPORT gpio_renesas_ra_ioport.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_RCAR gpio_rcar.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RA gpio_renesas_ra.c)
zephyr_library_sources_ifdef(CONFIG_GPIO_RPI_PICO gpio_rpi_pico.c)

2
drivers/gpio/Kconfig
View file

@ -155,7 +155,7 @@ source "drivers/gpio/Kconfig.pcf857x"
source "drivers/gpio/Kconfig.psoc6"
source "drivers/gpio/Kconfig.rcar"
source "drivers/gpio/Kconfig.renesas_ra"
source "drivers/gpio/Kconfig.renesas_ra8"
source "drivers/gpio/Kconfig.renesas_ra_ioport"
source "drivers/gpio/Kconfig.rpi_pico"
source "drivers/gpio/Kconfig.rt1718s"
source "drivers/gpio/Kconfig.rv32m1"

9
drivers/gpio/Kconfig.renesas_ra8
View file

@ -1,9 +0,0 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config GPIO_RA8
bool "Renesas RA8 GPIO driver"
default y
depends on DT_HAS_RENESAS_RA8_GPIO_ENABLED
help
Enable the Renesas RA8 GPIO driver.

9
drivers/gpio/Kconfig.renesas_ra_ioport Normal file
View file

@ -0,0 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config GPIO_RA_IOPORT
bool "Renesas RA GPIO IO port driver"
default y
depends on DT_HAS_RENESAS_RA_GPIO_IOPORT_ENABLED
help
Enable the Renesas RA GPIO IO port driver.

85
drivers/gpio/gpio_renesas_ra8.c → drivers/gpio/gpio_renesas_ra_ioport.c
View file

@ -4,29 +4,29 @@
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_ra8_gpio
#define DT_DRV_COMPAT renesas_ra_gpio_ioport
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/gpio/renesas-ra8-gpio.h>
#include <zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/irq.h>
#include <soc.h>
struct gpio_ra8_config {
struct gpio_ra_config {
struct gpio_driver_config common;
uint8_t port_num;
R_PORT0_Type *port;
gpio_pin_t vbatt_pins[];
};
struct gpio_ra8_data {
struct gpio_ra_data {
struct gpio_driver_data common;
};
static int gpio_ra8_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
{
const struct gpio_ra8_config *config = dev->config;
const struct gpio_ra_config *config = dev->config;
struct ra_pinctrl_soc_pin pincfg = {0};
@ -93,9 +93,9 @@ static int gpio_ra8_pin_configure(const struct device *dev, gpio_pin_t pin, gpio
return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE);
}
static int gpio_ra8_port_get_raw(const struct device *dev, uint32_t *value)
static int gpio_ra_port_get_raw(const struct device *dev, uint32_t *value)
{
const struct gpio_ra8_config *config = dev->config;
const struct gpio_ra_config *config = dev->config;
R_PORT0_Type *port = config->port;
*value = port->PIDR;
@ -103,10 +103,10 @@ static int gpio_ra8_port_get_raw(const struct device *dev, uint32_t *value)
return 0;
}
static int gpio_ra8_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
static int gpio_ra_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_ra8_config *config = dev->config;
const struct gpio_ra_config *config = dev->config;
R_PORT0_Type *port = config->port;
port->PODR = ((port->PODR & ~mask) | (value & mask));
@ -114,9 +114,9 @@ static int gpio_ra8_port_set_masked_raw(const struct device *dev, gpio_port_pins
return 0;
}
static int gpio_ra8_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
static int gpio_ra_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_ra8_config *config = dev->config;
const struct gpio_ra_config *config = dev->config;
R_PORT0_Type *port = config->port;
port->PODR = (port->PODR | pins);
@ -124,9 +124,9 @@ static int gpio_ra8_port_set_bits_raw(const struct device *dev, gpio_port_pins_t
return 0;
}
static int gpio_ra8_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
static int gpio_ra_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_ra8_config *config = dev->config;
const struct gpio_ra_config *config = dev->config;
R_PORT0_Type *port = config->port;
port->PODR = (port->PODR & ~pins);
@ -134,9 +134,9 @@ static int gpio_ra8_port_clear_bits_raw(const struct device *dev, gpio_port_pins
return 0;
}
static int gpio_ra8_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
static int gpio_ra_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
const struct gpio_ra8_config *config = dev->config;
const struct gpio_ra_config *config = dev->config;
R_PORT0_Type *port = config->port;
port->PODR = (port->PODR ^ pins);
@ -144,19 +144,19 @@ static int gpio_ra8_port_toggle_bits(const struct device *dev, gpio_port_pins_t
return 0;
}
static const struct gpio_driver_api gpio_ra8_drv_api_funcs = {
.pin_configure = gpio_ra8_pin_configure,
.port_get_raw = gpio_ra8_port_get_raw,
.port_set_masked_raw = gpio_ra8_port_set_masked_raw,
.port_set_bits_raw = gpio_ra8_port_set_bits_raw,
.port_clear_bits_raw = gpio_ra8_port_clear_bits_raw,
.port_toggle_bits = gpio_ra8_port_toggle_bits,
static const struct gpio_driver_api gpio_ra_drv_api_funcs = {
.pin_configure = gpio_ra_pin_configure,
.port_get_raw = gpio_ra_port_get_raw,
.port_set_masked_raw = gpio_ra_port_set_masked_raw,
.port_set_bits_raw = gpio_ra_port_set_bits_raw,
.port_clear_bits_raw = gpio_ra_port_clear_bits_raw,
.port_toggle_bits = gpio_ra_port_toggle_bits,
.pin_interrupt_configure = NULL,
.manage_callback = NULL,
};
#define GPIO_DEVICE_INIT(node, port_number, suffix, addr) \
static const struct gpio_ra8_config gpio_ra8_config_##suffix = { \
#define GPIO_DEVICE_INIT(node, port_number, suffix, addr) \
static const struct gpio_ra_config gpio_ra_config_##suffix = { \
.common = \
{ \
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(16U), \
@ -165,60 +165,59 @@ static const struct gpio_driver_api gpio_ra8_drv_api_funcs = {
.port = (R_PORT0_Type *)addr, \
.vbatt_pins = DT_PROP_OR(DT_NODELABEL(ioport##suffix), vbatts_pins, {0xFF}), \
}; \
static struct gpio_ra8_data gpio_ra8_data_##suffix; \
DEVICE_DT_DEFINE(node, NULL, NULL, &gpio_ra8_data_##suffix, \
&gpio_ra8_config_##suffix, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
&gpio_ra8_drv_api_funcs)
static struct gpio_ra_data gpio_ra_data_##suffix; \
DEVICE_DT_DEFINE(node, NULL, NULL, &gpio_ra_data_##suffix, &gpio_ra_config_##suffix, \
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_ra_drv_api_funcs)
#define GPIO_DEVICE_INIT_RA8(suffix) \
#define GPIO_DEVICE_INIT_RA(suffix) \
GPIO_DEVICE_INIT(DT_NODELABEL(ioport##suffix), \
DT_PROP(DT_NODELABEL(ioport##suffix), port), suffix, \
DT_REG_ADDR(DT_NODELABEL(ioport##suffix)))
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport0), okay)
GPIO_DEVICE_INIT_RA8(0);
GPIO_DEVICE_INIT_RA(0);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport0), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport1), okay)
GPIO_DEVICE_INIT_RA8(1);
GPIO_DEVICE_INIT_RA(1);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport1), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport2), okay)
GPIO_DEVICE_INIT_RA8(2);
GPIO_DEVICE_INIT_RA(2);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport2), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport3), okay)
GPIO_DEVICE_INIT_RA8(3);
GPIO_DEVICE_INIT_RA(3);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport3), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport4), okay)
GPIO_DEVICE_INIT_RA8(4);
GPIO_DEVICE_INIT_RA(4);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport4), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport5), okay)
GPIO_DEVICE_INIT_RA8(5);
GPIO_DEVICE_INIT_RA(5);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport5), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport6), okay)
GPIO_DEVICE_INIT_RA8(6);
GPIO_DEVICE_INIT_RA(6);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport6), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport7), okay)
GPIO_DEVICE_INIT_RA8(7);
GPIO_DEVICE_INIT_RA(7);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport7), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport8), okay)
GPIO_DEVICE_INIT_RA8(8);
GPIO_DEVICE_INIT_RA(8);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport8), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioport9), okay)
GPIO_DEVICE_INIT_RA8(9);
GPIO_DEVICE_INIT_RA(9);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioport9), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioporta), okay)
GPIO_DEVICE_INIT_RA8(a);
GPIO_DEVICE_INIT_RA(a);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioporta), okay) */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ioportb), okay)
GPIO_DEVICE_INIT_RA8(b);
GPIO_DEVICE_INIT_RA(b);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(ioportb), okay) */

24
dts/arm/renesas/ra/ra8/ra8x1.dtsi
View file

@ -50,7 +50,7 @@
};
ioport0: gpio@40400000 {
compatible = "renesas,ra8-gpio";
compatible = "renesas,ra-gpio-ioport";
reg = <0x40400000 0x20>;
port = <0>;
gpio-controller;
@ -60,7 +60,7 @@
};
ioport1: gpio@40400020 {
compatible = "renesas,ra8-gpio";
compatible = "renesas,ra-gpio-ioport";
reg = <0x40400020 0x20>;
port = <1>;
gpio-controller;
@ -70,7 +70,7 @@
};
ioport2: gpio@40400040 {
compatible = "renesas,ra8-gpio";
compatible = "renesas,ra-gpio-ioport";
reg = <0x40400040 0x20>;
port = <2>;
gpio-controller;
@ -80,7 +80,7 @@
};
ioport3: gpio@40400060 {
compatible = "renesas,ra8-gpio";
compatible = "renesas,ra-gpio-ioport";
reg = <0x40400060 0x20>;
port = <3>;
gpio-controller;
@ -90,7 +90,7 @@
};
ioport4: gpio@40400080 {
compatible = "renesas,ra8-gpio";
compatible = "renesas,ra-gpio-ioport";
reg = <0x40400080 0x20>;
port = <4>;
gpio-controller;
@ -101,7 +101,7 @@
};
ioport5: gpio@404000a0 {
compatible = "renesas,ra8-gpio";
compatible = "renesas,ra-gpio-ioport";
reg = <0x404000a0 0x20>;
port = <5>;
gpio-controller;
@ -111,7 +111,7 @@
};
ioport6: gpio@404000c0 {
compatible = "renesas,ra8-gpio";
compatible = "renesas,ra-gpio-ioport";
reg = <0x404000c0 0x20>;
port = <6>;
gpio-controller;
@ -121,7 +121,7 @@
};
ioport7: gpio@404000e0 {
compatible = "renesas,ra8-gpio";
compatible = "renesas,ra-gpio-ioport";
reg = <0x404000e0 0x20>;
port = <7>;
gpio-controller;
@ -131,7 +131,7 @@
};
ioport8: gpio@40400100 {
compatible = "renesas,ra8-gpio";
compatible = "renesas,ra-gpio-ioport";
reg = <0x40400100 0x20>;
port = <8>;
gpio-controller;
@ -141,7 +141,7 @@
};
ioport9: gpio@40400120 {
compatible = "renesas,ra8-gpio";
compatible = "renesas,ra-gpio-ioport";
reg = <0x40400120 0x20>;
port = <9>;
gpio-controller;
@ -151,7 +151,7 @@
};
ioporta: gpio@40400140 {
compatible = "renesas,ra8-gpio";
compatible = "renesas,ra-gpio-ioport";
reg = <0x40400140 0x20>;
port = <10>;
gpio-controller;
@ -161,7 +161,7 @@
};
ioportb: gpio@40400160 {
compatible = "renesas,ra8-gpio";
compatible = "renesas,ra-gpio-ioport";
reg = <0x40400160 0x20>;
port = <11>;
gpio-controller;

4
dts/bindings/gpio/renesas,ra8-gpio.yaml → dts/bindings/gpio/renesas,ra-gpio-ioport.yaml
View file

@ -1,9 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
description: Renesas RA8 GPIO
description: Renesas RA GPIO IO port
compatible: "renesas,ra8-gpio"
compatible: "renesas,ra-gpio-ioport"
include: [gpio-controller.yaml, base.yaml]

18
include/zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h Normal file
View file

@ -0,0 +1,18 @@
/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_
#define RENESAS_GPIO_DS_POS (8)
#define RENESAS_GPIO_DS_MSK (0x3U << RENESAS_GPIO_DS_POS)
/* GPIO Drive strength */
#define RENESAS_GPIO_DS_LOW (0x0 << RENESAS_GPIO_DRIVE_POS)
#define RENESAS_GPIO_DS_MIDDLE (0x1 << RENESAS_GPIO_DRIVE_POS)
#define RENESAS_GPIO_DS_HIGH_SPEED_HIGH_DRIVE (0x2 << RENESAS_GPIO_DRIVE_POS)
#define RENESAS_GPIO_DS_HIGH_DRIVE (0x3 << RENESAS_GPIO_DRIVE_POS)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_ */

18
include/zephyr/dt-bindings/gpio/renesas-ra8-gpio.h
View file

@ -1,18 +0,0 @@
/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA8_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA8_GPIO_H_
#define RENESAS_GPIO_DS_POS (8)
#define RENESAS_GPIO_DS_MSK (0x3U << RENESAS_GPIO_DS_POS)
/* GPIO Drive strength */
#define RENESAS_GPIO_DS_LOW (0x0 << RENESAS_GPIO_DRIVE_POS)
#define RENESAS_GPIO_DS_MIDDLE (0x1 << RENESAS_GPIO_DRIVE_POS)
#define RENESAS_GPIO_DS_HIGH_SPEED_HIGH_DRIVE (0x2 << RENESAS_GPIO_DRIVE_POS)
#define RENESAS_GPIO_DS_HIGH_DRIVE (0x3 << RENESAS_GPIO_DRIVE_POS)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA8_GPIO_H_ */