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dts: mpfs_icicle: add cpu nodes

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Microchip's PolarFire SoC has a core complex consisting of one e51
monitor core and four u54 application cores. Add the remaining cpu nodes
to mpfs-icicle device tree. Add the software and timer interrupt irq's
to the clint for the additional cpu nodes.

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
This commit is contained in:
Conor Paxton 2023-01-16 13:37:46 +00:00 committed by Carles Cufí
parent 650b244215
commit 978a0eba21
1 changed files with 49 additions and 2 deletions
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51
dts/riscv/mpfs-icicle.dtsi
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@ -41,6 +41,48 @@
interrupt-controller;
};
};
cpu@2 {
clock-frequency = <0>;
compatible = "microsemi,miv", "riscv";
device_type = "cpu";
reg = < 0x2 >;
riscv,isa = "rv64imafdc";
hlic2: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu@3 {
clock-frequency = <0>;
compatible = "microsemi,miv", "riscv";
device_type = "cpu";
reg = < 0x3 >;
riscv,isa = "rv64imafdc";
hlic3: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu@4 {
clock-frequency = <0>;
compatible = "microsemi,miv", "riscv";
device_type = "cpu";
reg = < 0x4 >;
riscv,isa = "rv64imafdc";
hlic4: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
};
soc {
@ -62,8 +104,13 @@
clint: clint@2000000 {
compatible = "sifive,clint0";
interrupts-extended = <&hlic0 3 &hlic0 7
&hlic1 3 &hlic1 7>;
interrupt-names = "soft0", "timer0", "soft1", "timer1";
&hlic1 3 &hlic1 7
&hlic2 3 &hlic2 7
&hlic3 3 &hlic3 7
&hlic4 3 &hlic4 7>;
interrupt-names = "soft0", "timer0", "soft1", "timer1",
"soft2", "timer2", "soft3", "timer3",
"soft4", "timer4";
reg = <0x2000000 0x10000>;
};