soc: ti_k3: Add TI J722s SoC MAIN R5
Add initial SoC support for the TI J722s SoC series MAIN-domain Cortex-R5 core. TRM for J722s: https://www.ti.com/lit/zip/sprujb3 Signed-off-by: Andrew Davis <afd@ti.com>
This commit is contained in:
Andrew Davis
Benjamin Cabé
parent
01d9861d71
commit
9af843e269
4 changed files with 177 additions and 0 deletions
109
dts/arm/ti/j722s_main.dtsi
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109
dts/arm/ti/j722s_main.dtsi
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@ -0,0 +1,109 @@
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/*
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* Copyright (c) 2024 Texas Instruments Incorporated
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* Andrew Davis <afd@ti.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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pinctrl: pinctrl@f4000 {
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compatible = "ti,k3-pinctrl";
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reg = <0x000f4000 0x2ac>;
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status = "okay";
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};
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gpio0: gpio@600010 {
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compatible = "ti,davinci-gpio";
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reg = <0x00600010 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <92>;
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status = "disabled";
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};
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gpio1: gpio@601010 {
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compatible = "ti,davinci-gpio";
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reg = <0x00601010 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <52>;
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status = "disabled";
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};
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uart0: uart@2800000 {
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compatible = "ns16550";
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reg = <0x02800000 0x100>;
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clock-frequency = <48000000>;
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interrupts = <0 210 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&vim>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart1: uart@2810000 {
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compatible = "ns16550";
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reg = <0x02810000 0x100>;
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clock-frequency = <48000000>;
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interrupts = <0 211 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&vim>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: uart@2820000 {
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compatible = "ns16550";
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reg = <0x02820000 0x100>;
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clock-frequency = <48000000>;
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interrupts = <0 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&vim>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart3: uart@2830000 {
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compatible = "ns16550";
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reg = <0x02830000 0x100>;
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clock-frequency = <48000000>;
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interrupts = <0 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&vim>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart4: uart@2840000 {
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compatible = "ns16550";
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reg = <0x02840000 0x100>;
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clock-frequency = <48000000>;
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interrupts = <0 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&vim>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart5: uart@2850000 {
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compatible = "ns16550";
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reg = <0x02850000 0x100>;
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clock-frequency = <48000000>;
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interrupts = <0 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&vim>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart6: uart@2860000 {
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compatible = "ns16550";
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reg = <0x02860000 0x100>;
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clock-frequency = <48000000>;
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interrupts = <0 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&vim>;
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reg-shift = <2>;
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status = "disabled";
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};
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};
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60
dts/arm/ti/j722s_main_r5.dtsi
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60
dts/arm/ti/j722s_main_r5.dtsi
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@ -0,0 +1,60 @@
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/*
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* Copyright (c) 2024 Texas Instruments Incorporated
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* Andrew Davis <afd@ti.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <arm/armv7-r.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
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#include "j722s_main.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r5";
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reg = <0>;
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};
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};
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atcm: memory@0 {
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device_type = "memory";
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x00000000 DT_SIZE_K(32)>;
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zephyr,memory-region = "ATCM";
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};
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btcm: memory@41010000 {
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device_type = "memory";
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x41010000 DT_SIZE_K(32)>;
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zephyr,memory-region = "BTCM";
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};
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vim: interrupt-controller@2fff0000 {
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#address-cells = <1>;
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compatible = "ti,vim";
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reg = <0x2fff0000 0x2800>;
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interrupt-controller;
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#interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */
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status = "okay";
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};
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systick_timer: timer@2470000 {
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compatible = "ti,am654-timer";
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reg = <0x02470000 0x70>;
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interrupts = <0 35 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&vim>;
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status = "disabled";
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};
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};
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@ -39,6 +39,10 @@ config SOC_J721E_MAIN_R5F0_0
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bool
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select SOC_SERIES_AM6X_R5
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config SOC_J722S_MAIN_R5F0_0
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bool
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select SOC_SERIES_AM6X_R5
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config SOC_SERIES
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default "am6x" if SOC_SERIES_AM6X
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@ -46,3 +50,4 @@ config SOC
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default "am6234" if SOC_AM6234_M4 || SOC_AM6234_A53
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default "am6442" if SOC_AM6442_M4
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default "j721e" if SOC_J721E_MAIN_R5F0_0
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default "j722s" if SOC_J722S_MAIN_R5F0_0
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@ -13,3 +13,6 @@ family:
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- name: j721e
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cpuclusters:
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- name: main_r5f0_0
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- name: j722s
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cpuclusters:
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- name: main_r5f0_0
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