From 9c574ed9222b331403f684b235e476700a9b1854 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20St=C4=99pnicki?= Date: Thu, 16 Jan 2025 09:36:08 +0100 Subject: [PATCH] arch: riscv: option to init custom hw stacked esf members. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When RISCV_SOC_HAS_ISR_STACKING is used, it may be needed to initialize custom hw stacked esf members. Some initial values may need to be aligned with hw stacking mechanism to avoid any side effects. Signed-off-by: Łukasz Stępnicki --- arch/riscv/Kconfig | 5 +++++ arch/riscv/core/thread.c | 4 ++++ soc/nordic/common/vpr/soc_isr_stacking.h | 7 +++++++ 3 files changed, 16 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b70eb0aca14..83e3ef86d07 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -124,6 +124,11 @@ config RISCV_SOC_HAS_ISR_STACKING saved on the stack by the hardware, and the registers saved by the software macros. The structure must be called 'struct arch_esf'. + - SOC_ISR_STACKING_ESR_INIT: macro guarded by !_ASMLANGUAGE. + Some hardware stacked registers should be initialized on init + stack with proper values. This prevents from incorrect behavior + on entry context switch when initial stack is restored. + config RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING bool help diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c index b4999bda09a..896f8e5199d 100644 --- a/arch/riscv/core/thread.c +++ b/arch/riscv/core/thread.c @@ -106,6 +106,10 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, stack_init->soc_context = soc_esf_init; #endif +#ifdef CONFIG_RISCV_SOC_HAS_ISR_STACKING + SOC_ISR_STACKING_ESR_INIT; +#endif + thread->callee_saved.sp = (unsigned long)stack_init; /* where to go when returning from z_riscv_switch() */ diff --git a/soc/nordic/common/vpr/soc_isr_stacking.h b/soc/nordic/common/vpr/soc_isr_stacking.h index 014ae1296a0..c5f0e7b2762 100644 --- a/soc/nordic/common/vpr/soc_isr_stacking.h +++ b/soc/nordic/common/vpr/soc_isr_stacking.h @@ -60,6 +60,13 @@ #endif /* DT_PROP(VPR_CPU, nordic_bus_width) == 64 */ +/* + * VPR stacked mcause needs to have proper value on initial stack. + * Initial mret will restore this value. + */ +#define SOC_ISR_STACKING_ESR_INIT \ + stack_init->_mcause = 0; + #else /* _ASMLANGUAGE */ /*