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dts: Add support for additional modules in STM32U0.

Browse source 
This commit Introduces DTS configurations for DMA,
SPI, RNG, Crypto, USB and RTC modules to enable
support in STM32U0.

Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
This commit is contained in:
Sara Touqan 2024-11-26 15:32:53 +02:00 committed by Benjamin Cabé
parent 44e5f952ac
commit a0380bc61d
3 changed files with 189 additions and 0 deletions
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137
dts/arm/st/u0/stm32u0.dtsi
View file

@ -12,6 +12,7 @@
#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
#include <zephyr/dt-bindings/dma/stm32_dma.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/reset/stm32u0_reset.h>
#include <freq.h>
@ -19,6 +20,7 @@
/ {
chosen {
zephyr,flash-controller = &flash;
zephyr,entropy = &rng;
};
cpus {
@ -213,6 +215,38 @@
status = "disabled";
};
lpuart1: serial@40008000 {
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
resets = <&rctl STM32_RESET(APB1L, 20U)>;
interrupts = <28 0>;
status = "disabled";
};
lpuart2: serial@40008400 {
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
resets = <&rctl STM32_RESET(APB1L, 7U)>;
interrupts = <29 0>;
status = "disabled";
};
iwdg: watchdog@40003000 {
compatible = "st,stm32-watchdog";
reg = <0x40003000 0x400>;
status = "disabled";
};
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
interrupts = <0 7>;
status = "disabled";
};
adc1: adc@40012400 {
compatible = "st,stm32-adc";
reg = <0x40012400 0x400>;
@ -274,6 +308,86 @@
status = "disabled";
};
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2";
#dma-cells = <3>;
reg = <0x40020000 0x400>;
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
dma-requests = <7>;
dma-offset = <0>;
status = "disabled";
};
dmamux1: dmamux@40020800 {
compatible = "st,stm32-dmamux";
#dma-cells = <3>;
reg = <0x40020800 0x400>;
interrupts = <11 0>;
dma-channels = <7>;
dma-generators = <4>;
dma-requests= <76>;
status = "disabled";
};
spi1: spi@40013000 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 12U)>;
interrupts = <25 0>;
status = "disabled";
};
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
interrupts = <26 0>;
status = "disabled";
};
spi3: spi@40003c00 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
interrupts = <26 0>;
status = "disabled";
};
rng: rng@40025000 {
compatible = "st,stm32-rng";
reg = <0x40025000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
interrupts = <31 0>;
status = "disabled";
};
aes: aes@40026000 {
compatible = "st,stm32-aes";
reg = <0x40026000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB1, 16U)>;
resets = <&rctl STM32_RESET(AHB1, 16U)>;
interrupts = <31 0>;
interrupt-names = "aes";
status = "disabled";
};
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
interrupts = <2 0>;
clocks = <&rcc STM32_CLOCK(APB1, 10U)>;
prescaler = <32768>;
alarms-count = <2>;
alrm-exti-line = <28>;
status = "disabled";
};
timers1: timers@40012c00 {
compatible = "st,stm32-timers";
@ -406,6 +520,29 @@
status = "disabled";
};
};
lptim1: timers@40007c00 {
compatible = "st,stm32-lptim";
clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40007c00 0x400>;
interrupts = <17 1>;
interrupt-names = "combined";
status = "disabled";
};
lptim2: timers@40009400 {
compatible = "st,stm32-lptim";
clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40009400 0x400>;
interrupts = <18 1>;
interrupt-names = "combined";
status = "disabled";
};
};
};

43
dts/arm/st/u0/stm32u073.dtsi
View file

@ -21,6 +21,49 @@
interrupt-names = "combined";
status = "disabled";
};
lptim3: timers@40009000 {
compatible = "st,stm32-lptim";
clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40009000 0x400>;
interrupts = <19 1>;
interrupt-names = "combined";
status = "disabled";
};
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2";
#dma-cells = <3>;
reg = <0x40020400 0x400>;
interrupts = <11 0 11 0 11 0 11 0 11 0>;
clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
dma-requests = <5>;
dma-offset = <7>;
status = "disabled";
};
dmamux1: dmamux@40020800 {
dma-channels = <12>;
};
usb: usb@40005c00 {
compatible = "st,stm32-usb";
reg = <0x40005c00 0x400>;
interrupts = <8 0>;
interrupt-names = "usb";
num-bidir-endpoints = <8>;
ram-size = <1024>;
phys = <&usb_fs_phy>;
clocks = <&rcc STM32_CLOCK(APB1, 13U)>;
status = "disabled";
};
usb_fs_phy: usbphy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};
sram1: memory@20000000 {

9
dts/arm/st/u0/stm32u083.dtsi
View file

@ -9,5 +9,14 @@
/ {
soc {
compatible = "st,stm32u083", "st,stm32u0", "simple-bus";
lpuart3: serial@40008c00 {
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 12U)>;
resets = <&rctl STM32_RESET(APB1L, 12U)>;
interrupts = <30 0>;
status = "disabled";
};
};
};