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adc: mec15xx: add pinctrl for mec15xx/mec1501 adc

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Remove pinmux calls and add pinctrl support for mec15xx
and mec1501 adc. Update board dts, pinmux and driver files.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
This commit is contained in:
Jay Vasanth 2022-09-21 11:22:26 -04:00 committed by Fabio Baltieri
parent 53e6da72d4
commit a2de15e5cc
6 changed files with 35 additions and 44 deletions
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4
boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.dts
View file

@ -56,6 +56,10 @@
&adc0 {
status = "okay";
pinctrl-0 = <&adc04_gpio204 &adc05_gpio205
&adc06_gpio206 &adc07_gpio207
&vref2_adc_gpio067 >;
pinctrl-names = "default";
};
&i2c_smb_0 {

21
boards/arm/mec1501modular_assy6885/pinmux.c
View file

@ -150,27 +150,6 @@ static int board_pinmux_init(const struct device *dev)
pinmux_pin_set(portd, MCHP_GPIO_171, MCHP_GPIO_CTRL_MUX_F1);
#endif
#ifdef CONFIG_ADC_XEC
/* Disable sleep for ADC block */
mchp_pcr_periph_slp_ctrl(PCR_ADC, MCHP_PCR_SLEEP_DIS);
/* ADC pin muxes, ADC00 - ADC07 */
/* Note, by default ETM is enabled ADC00-ADC03 are not available */
#ifndef CONFIG_SOC_MEC1501_DEBUG_AND_ETM_TRACING
pinmux_pin_set(porte, MCHP_GPIO_200, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_201, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_202, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_203, MCHP_GPIO_CTRL_MUX_F1);
#endif
pinmux_pin_set(porte, MCHP_GPIO_204, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_205, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_206, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_207, MCHP_GPIO_CTRL_MUX_F1);
/* VREF2_ADC */
pinmux_pin_set(portb, MCHP_GPIO_067, MCHP_GPIO_CTRL_MUX_F1);
#endif /* CONFIG_ADC_XEC */
#ifdef CONFIG_SPI_XEC_QMSPI
#if DT_NODE_HAS_STATUS(DT_INST(0, microchip_xec_qmspi), okay)
mchp_pcr_periph_slp_ctrl(PCR_QMSPI, MCHP_PCR_SLEEP_DIS);

4
boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853.dts
View file

@ -84,6 +84,10 @@
&adc0 {
status = "okay";
pinctrl-0 = <&adc04_gpio204 &adc05_gpio205
&adc06_gpio206 &adc07_gpio207
&vref2_adc_gpio067 >;
pinctrl-names = "default";
};
&i2c_smb_0 {

21
boards/arm/mec15xxevb_assy6853/pinmux.c
View file

@ -140,27 +140,6 @@ static int board_pinmux_init(const struct device *dev)
pinmux_pin_set(portd, MCHP_GPIO_146, MCHP_GPIO_CTRL_MUX_F2);
#endif
#ifdef CONFIG_ADC_XEC
/* Disable sleep for ADC block */
mchp_pcr_periph_slp_ctrl(PCR_ADC, MCHP_PCR_SLEEP_DIS);
/* ADC pin muxes, ADC00 - ADC07 */
/* Note, by default ETM is enabled ADC00-ADC03 are not available */
#ifndef CONFIG_SOC_MEC1501_DEBUG_AND_ETM_TRACING
pinmux_pin_set(porte, MCHP_GPIO_200, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_201, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_202, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_203, MCHP_GPIO_CTRL_MUX_F1);
#endif
pinmux_pin_set(porte, MCHP_GPIO_204, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_205, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_206, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_207, MCHP_GPIO_CTRL_MUX_F1);
/* VREF2_ADC */
pinmux_pin_set(portb, MCHP_GPIO_067, MCHP_GPIO_CTRL_MUX_F1);
#endif /* CONFIG_ADC_XEC */
#ifdef CONFIG_SPI_XEC_QMSPI
#if DT_NODE_HAS_STATUS(DT_INST(0, microchip_xec_qmspi), okay)
mchp_pcr_periph_slp_ctrl(PCR_QMSPI, MCHP_PCR_SLEEP_DIS);

21
drivers/adc/adc_mchp_xec.c
View file

@ -11,6 +11,7 @@
LOG_MODULE_REGISTER(adc_mchp_xec);
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#include <errno.h>
@ -28,6 +29,10 @@ LOG_MODULE_REGISTER(adc_mchp_xec);
#define XEC_ADC_CTRL_START_SINGLE BIT(1)
#define XEC_ADC_CTRL_ACTIVATE BIT(0)
struct adc_xec_config {
const struct pinctrl_dev_config *pcfg;
};
struct adc_xec_data {
struct adc_context ctx;
uint16_t *buffer;
@ -285,8 +290,16 @@ struct adc_driver_api adc_xec_api = {
static int adc_xec_init(const struct device *dev)
{
const struct adc_xec_config *const cfg = dev->config;
struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE;
struct adc_xec_data *data = dev->data;
int ret;
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("XEC ADC pinctrl setup failed (%d)", ret);
return ret;
}
adc_regs->config_reg = XEC_ADC_CFG_CLK_VAL(DT_INST_PROP(0, clktime));
@ -308,6 +321,12 @@ static int adc_xec_init(const struct device *dev)
return 0;
}
PINCTRL_DT_INST_DEFINE(0);
static struct adc_xec_config adc_xec_dev_cfg_0 = {
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
};
static struct adc_xec_data adc_xec_dev_data_0 = {
ADC_CONTEXT_INIT_TIMER(adc_xec_dev_data_0, ctx),
ADC_CONTEXT_INIT_LOCK(adc_xec_dev_data_0, ctx),
@ -315,6 +334,6 @@ static struct adc_xec_data adc_xec_dev_data_0 = {
};
DEVICE_DT_INST_DEFINE(0, adc_xec_init, NULL,
&adc_xec_dev_data_0, NULL,
&adc_xec_dev_data_0, &adc_xec_dev_cfg_0,
PRE_KERNEL_1, CONFIG_ADC_INIT_PRIORITY,
&adc_xec_api);

8
dts/bindings/adc/microchip,xec-adc.yaml
View file

@ -5,7 +5,7 @@ description: Microchip XEC ADC
compatible: "microchip,xec-adc"
include: adc-controller.yaml
include: [adc-controller.yaml, pinctrl-device.yaml]
properties:
reg:
@ -22,5 +22,11 @@ properties:
required: true
description: ADC clock high & low time count value <1:255>
pinctrl-0:
required: true
pinctrl-names:
required: true
io-channel-cells:
- input