dts: microchip: mec5: Base MEC5 MEC174x, MEC1752, MECH172x DTSI files
Add the base DTSI chip files for Microchip MEC174x, MEC175x, and MECH172x using new MEC5 HAL. Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
Scott Worley
Anas Nashif
parent
36c9fdcb85
commit
a698b77fb4
15 changed files with 1028 additions and 0 deletions
651
dts/arm/microchip/mec5.dtsi
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651
dts/arm/microchip/mec5.dtsi
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/*
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* Copyright (c) 2024 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <freq.h>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4";
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reg = <0>;
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};
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};
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soc {
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ecs: ecs@4000fc00 {
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reg = <0x4000fc00 0x200>;
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status = "disabled";
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};
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pcr: pcr@40080100 {
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reg = <0x40080100 0x100 0x4000a400 0x100>;
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reg-names = "pcrr", "vbatr";
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interrupts = <174 0>;
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status = "disabled";
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};
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ecia: ecia@4000e000 {
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reg = <0x4000e000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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ranges = <0x0 0x4000e000 0x400>;
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girq8: girq8@0 {
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reg = <0x0 0x14>;
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interrupts = <0 1>;
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status = "disabled";
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};
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girq9: girq9@14 {
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reg = <0x14 0x14>;
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interrupts = <1 1>;
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status = "disabled";
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};
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girq10: girq10@28 {
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reg = <0x28 0x14>;
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interrupts = <2 1>;
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status = "disabled";
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};
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girq11: girq11@3c {
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reg = <0x3c 0x14>;
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interrupts = <3 1>;
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status = "disabled";
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};
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girq12: girq12@50 {
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reg = <0x50 0x14>;
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interrupts = <4 1>;
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status = "disabled";
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};
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girq13: girq13@64 {
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reg = <0x64 0x14>;
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interrupts = <5 1>;
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status = "disabled";
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};
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girq14: girq14@78 {
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reg = <0x78 0x14>;
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interrupts = <6 1>;
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status = "disabled";
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};
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girq15: girq15@8c {
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reg = <0x8c 0x14>;
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interrupts = <7 1>;
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status = "disabled";
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};
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girq16: girq16@a0 {
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reg = <0xa0 0x14>;
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interrupts = <8 1>;
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status = "disabled";
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};
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girq17: girq17@b4 {
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reg = <0xb4 0x14>;
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interrupts = <9 1>;
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status = "disabled";
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};
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girq18: girq18@c8 {
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reg = <0xc8 0x14>;
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interrupts = <10 1>;
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status = "disabled";
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};
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girq19: girq19@dc {
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reg = <0xdc 0x14>;
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interrupts = <11 1>;
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status = "disabled";
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};
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girq20: girq20@f0 {
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reg = <0xf0 0x14>;
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interrupts = <12 1>;
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status = "disabled";
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};
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girq21: girq21@104 {
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reg = <0x104 0x14>;
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interrupts = <13 1>;
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status = "disabled";
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};
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girq22: girq22@118 {
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reg = <0x118 0x14>;
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interrupts = <255 0>;
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status = "disabled";
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};
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girq23: girq23@12c {
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reg = <0x12c 0x14>;
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interrupts = <14 1>;
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status = "disabled";
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};
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girq24: girq24@140 {
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reg = <0x140 0x14>;
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interrupts = <15 1>;
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status = "disabled";
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};
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girq25: girq25@154 {
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reg = <0x154 0x14>;
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interrupts = <16 1>;
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status = "disabled";
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};
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girq26: girq26@168 {
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reg = <0x168 0x14>;
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interrupts = <17 1>;
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status = "disabled";
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};
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};
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pinctrl: pin-controller@40081000 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40081000 0x1000>;
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gpio_000_036: gpio@40081000 {
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reg = < 0x40081000 0x80 0x40081300 0x04
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0x40081380 0x04 0x400813fc 0x04>;
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interrupts = <3 2>;
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gpio-controller;
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port-id = <0>;
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girq-id = <11>;
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#gpio-cells=<2>;
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};
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gpio_040_076: gpio@40081080 {
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reg = < 0x40081080 0x80 0x40081304 0x04
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0x40081384 0x04 0x400813f8 0x4>;
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interrupts = <2 2>;
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gpio-controller;
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port-id = <1>;
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girq-id = <10>;
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#gpio-cells=<2>;
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};
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gpio_100_136: gpio@40081100 {
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reg = < 0x40081100 0x80 0x40081308 0x04
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0x40081388 0x04 0x400813f4 0x04>;
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gpio-controller;
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interrupts = <1 2>;
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port-id = <2>;
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girq-id = <9>;
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#gpio-cells=<2>;
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};
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gpio_140_176: gpio@40081180 {
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reg = < 0x40081180 0x80 0x4008130c 0x04
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0x4008138c 0x04 0x400813f0 0x04>;
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gpio-controller;
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interrupts = <0 2>;
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port-id = <3>;
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girq-id = <8>;
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#gpio-cells=<2>;
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};
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gpio_200_236: gpio@40081200 {
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reg = < 0x40081200 0x80 0x40081310 0x04
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0x40081390 0x04 0x400813ec 0x04>;
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gpio-controller;
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interrupts = <4 2>;
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port-id = <4>;
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girq-id = <12>;
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#gpio-cells=<2>;
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};
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gpio_240_276: gpio@40081280 {
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reg = < 0x40081280 0x80 0x40081314 0x04
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0x40081394 0x04 0x400813e8 0x04>;
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gpio-controller;
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interrupts = <17 2>;
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port-id = <5>;
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girq-id = <26>;
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#gpio-cells=<2>;
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};
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};
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uart0: uart@400f2400 {
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reg = <0x400f2400 0x400>;
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interrupts = <40 1>;
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status = "disabled";
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};
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uart1: uart@400f2800 {
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reg = <0x400f2800 0x400>;
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interrupts = <41 1>;
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status = "disabled";
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};
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wdog: watchdog@40000400 {
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reg = <0x40000400 0x400>;
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interrupts = <171 0>;
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status = "disabled";
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};
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rtimer: timer@40007400 {
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reg = <0x40007400 0x10>;
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interrupts = <111 0>;
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clock-frequency = <32768>;
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max-value = <0xffffffff>;
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status = "disabled";
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};
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timer0: timer@40000c00 {
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reg = <0x40000c00 0x20>;
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interrupts = <136 0>;
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clock-frequency = <48000000>;
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prescaler = <0>;
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max-value = <0xffff>;
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status = "disabled";
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};
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timer1: timer@40000c20 {
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reg = <0x40000c20 0x20>;
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interrupts = <137 0>;
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clock-frequency = <48000000>;
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prescaler = <0>;
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max-value = <0xffff>;
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status = "disabled";
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};
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timer2: timer@40000c40 {
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reg = <0x40000c40 0x20>;
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interrupts = <138 0>;
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clock-frequency = <48000000>;
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prescaler = <0>;
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max-value = <0xffff>;
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status = "disabled";
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};
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timer3: timer@40000c60 {
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reg = <0x40000c60 0x20>;
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interrupts = <139 0>;
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clock-frequency = <48000000>;
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prescaler = <0>;
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max-value = <0xffff>;
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status = "disabled";
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};
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timer4: timer@40000c80 {
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reg = <0x40000c80 0x20>;
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interrupts = <140 0>;
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clock-frequency = <48000000>;
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prescaler = <0>;
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max-value = <0xffffffff>;
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status = "disabled";
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};
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timer5: timer@40000ca0 {
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reg = <0x40000ca0 0x20>;
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interrupts = <141 0>;
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clock-frequency = <48000000>;
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prescaler = <0>;
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max-value = <0xffffffff>;
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status = "disabled";
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};
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cntr0: timer@40000d00 {
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reg = <0x40000d00 0x20>;
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interrupts = <142 0>;
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status = "disabled";
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};
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cntr1: timer@40000d20 {
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reg = <0x40000d20 0x20>;
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interrupts = <143 0>;
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status = "disabled";
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};
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cntr2: timer@40000d40 {
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reg = <0x40000d40 0x20>;
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interrupts = <144 0>;
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status = "disabled";
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};
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cntr3: timer@40000d60 {
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reg = <0x40000d60 0x20>;
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interrupts = <145 0>;
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status = "disabled";
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};
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cctmr0: timer@40001000 {
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reg = <0x40001000 0x40>;
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interrupts = <146 0>, <147 0>, <148 0>, <149 0>,
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<150 0>, <151 0>, <152 0>, <153 0>,
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<154 0>;
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status = "disabled";
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};
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hibtimer0: timer@40009800 {
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reg = <0x40009800 0x20>;
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interrupts = <112 0>;
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status = "disabled";
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};
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hibtimer1: timer@40009820 {
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reg = <0x40009820 0x20>;
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interrupts = <113 0>;
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status = "disabled";
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};
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weektmr0: timer@4000ac80 {
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reg = <0x4000ac80 0x80>;
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interrupts = <114 0>, <115 0>, <116 0>,
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<117 0>, <118 0>;
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status = "disabled";
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};
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rtc0: rtc@400f5000 {
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reg = <0x400f5000 0x100>;
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interrupts = <119 3>, <120 3>;
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status = "disabled";
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};
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bbram: bb-ram@4000a800 {
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reg = <0x4000a800 0x100>;
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reg-names = "memory";
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status = "disabled";
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};
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vci0: vci@4000ae00 {
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reg = <0x4000ae00 0x40>;
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interrupts = <121 0>, <122 0>, <123 0>,
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<124 0>, <125 0>;
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status = "disabled";
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};
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i2c_smb_0: i2c@40004000 {
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reg = <0x40004000 0x80>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <20 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c_smb_1: i2c@40004400 {
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reg = <0x40004400 0x80>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <21 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c_smb_2: i2c@40004800 {
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reg = <0x40004800 0x80>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <22 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c_smb_3: i2c@40004c00 {
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reg = <0x40004C00 0x80>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <23 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c_smb_4: i2c@40005000 {
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reg = <0x40005000 0x80>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <158 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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ps2_0: ps2@40009000 {
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reg = <0x40009000 0x40>;
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interrupts = <100 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pwm0: pwm@40005800 {
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reg = <0x40005800 0x10>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm1: pwm@40005810 {
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reg = <0x40005810 0x10>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm2: pwm@40005820 {
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reg = <0x40005820 0x10>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm3: pwm@40005830 {
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reg = <0x40005830 0x10>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm4: pwm@40005840 {
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reg = <0x40005840 0x10>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm5: pwm@40005850 {
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reg = <0x40005850 0x10>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm6: pwm@40005860 {
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reg = <0x40005860 0x10>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm7: pwm@40005870 {
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reg = <0x40005870 0x10>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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pwm8: pwm@40005880 {
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reg = <0x40005880 0x10>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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tach0: tach@40006000 {
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reg = <0x40006000 0x10>;
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interrupts = <71 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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tach1: tach@40006010 {
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reg = <0x40006010 0x10>;
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interrupts = <72 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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tach2: tach@40006020 {
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reg = <0x40006020 0x10>;
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interrupts = <73 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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tach3: tach@40006030 {
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reg = <0x40006030 0x10>;
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interrupts = <159 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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rpmfan0: rpmfan@4000a000 {
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reg = <0x4000a000 0x80>;
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interrupts = <74 1>, <75 1>;
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status = "disabled";
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};
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rpmfan1: rpmfan@4000a080 {
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reg = <0x4000a080 0x80>;
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interrupts = <76 1>, <77 1>;
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status = "disabled";
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};
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adc0: adc@40007c00 {
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reg = <0x40007c00 0x90>;
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interrupts = <78 0>, <79 0>;
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interrupt-names = "single", "repeat";
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status = "disabled";
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#io-channel-cells = <1>;
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clktime = <32>;
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};
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peci0: peci@40006400 {
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reg = <0x40006400 0x80>;
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interrupts = <70 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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qspi0: spi@40070000 {
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reg = <0x40070000 0x400>;
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interrupts = <91 2>;
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clock-frequency = <12000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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prochot0: prochot@40003400 {
|
||||
reg = <0x40003400 0x20>;
|
||||
interrupts = <87 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
rcid0: rcid@40001400 {
|
||||
reg = <0x40001400 0x80>;
|
||||
interrupts = <80 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
rcid1: rcid@40001480 {
|
||||
reg = <0x40001480 0x80>;
|
||||
interrupts = <81 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
rcid2: rcid@40001500 {
|
||||
reg = <0x40001500 0x80>;
|
||||
interrupts = <82 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
bbled0: bbled@4000b800 {
|
||||
reg = <0x4000b800 0x100>;
|
||||
interrupts = <83 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
bbled1: bbled@4000b900 {
|
||||
reg = <0x4000b900 0x100>;
|
||||
interrupts = <84 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
bbled2: bbled@4000ba00 {
|
||||
reg = <0x4000ba00 0x100>;
|
||||
interrupts = <85 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
bbled3: bbled@4000bb00 {
|
||||
reg = <0x4000bb00 0x100>;
|
||||
interrupts = <86 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
bclink0: bclink@4000cd00 {
|
||||
reg = <0x4000cd00 0x20>;
|
||||
interrupts = <96 0>, <97 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
tfdp0: tfdp@40008c00 {
|
||||
reg = <0x40008c00 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
glblcfg0: glblcfg@400fff00 {
|
||||
reg = <0x400fff00 0x40>;
|
||||
status = "disabled";
|
||||
};
|
||||
espi0: espi@400f3400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = < 0x400f3400 0x400
|
||||
0x400f3800 0x400
|
||||
0x400f9c00 0x400>;
|
||||
reg-names = "io", "mem", "vw";
|
||||
interrupts = <103 3>, <104 3>, <105 3>, <106 3>,
|
||||
<107 3>, <108 3>, <109 3>, <110 2>,
|
||||
<156 3>, <15 3>, <16 3>;
|
||||
interrupt-names = "pc", "bm1", "bm2", "ltr", "oob_up",
|
||||
"oob_dn", "fc", "erst", "vw_chan_en",
|
||||
"vwct_0_6", "vwct_7_10";
|
||||
status = "disabled";
|
||||
|
||||
/* Devices accessible to the Host via Logical Device mechanism.
|
||||
* Some devices are capable of having their registers mapped to
|
||||
* Host I/O or memory address space. Some devices are capable
|
||||
* of generating Serial IRQ to the Host over eSPI.
|
||||
*/
|
||||
mbox0: mbox@400f0000 {
|
||||
reg = <0x400f0000 0x200>;
|
||||
interrupts = <60 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
kbc0: kbc@400f0400 {
|
||||
reg = <0x400f0400 0x400>, <0x400f2000 0x400>;
|
||||
interrupts = <59 3>, <58 3>;
|
||||
interrupt-names = "ibf", "obe";
|
||||
status = "disabled";
|
||||
};
|
||||
acpi_ec0: acpi_ec@400f0800 {
|
||||
reg = <0x400f0800 0x400>;
|
||||
interrupts = <45 3>, <46 3>;
|
||||
interrupt-names = "ibf", "obe";
|
||||
status = "disabled";
|
||||
};
|
||||
acpi_ec1: acpi_ec@400f0c00 {
|
||||
reg = <0x400f0c00 0x400>;
|
||||
interrupts = <47 3>, <48 3>;
|
||||
interrupt-names = "ibf", "obe";
|
||||
status = "disabled";
|
||||
};
|
||||
acpi_ec2: acpi_ec@400f1000 {
|
||||
reg = <0x400f1000 0x400>;
|
||||
interrupts = <49 3>, <50 3>;
|
||||
interrupt-names = "ibf", "obe";
|
||||
status = "disabled";
|
||||
};
|
||||
acpi_ec3: acpi_ec@400f1400 {
|
||||
reg = <0x400f1400 0x400>;
|
||||
interrupts = <51 3>, <52 3>;
|
||||
interrupt-names = "ibf", "obe";
|
||||
status = "disabled";
|
||||
};
|
||||
acpi_ec4: acpi_ec@400f1800 {
|
||||
reg = <0x400f1800 0x400>;
|
||||
interrupts = <53 3>, <54 3>;
|
||||
interrupt-names = "ibf", "obe";
|
||||
status = "disabled";
|
||||
};
|
||||
acpi_pm1: acpi_pm1@400f1c00 {
|
||||
reg = <0x400f1c00 0x400>;
|
||||
interrupts = <55 3>, <56 3>, <57 3>;
|
||||
interrupt-names = "ctl", "en", "sts";
|
||||
status = "disabled";
|
||||
};
|
||||
glue: glue_logic@400f3c00 {
|
||||
reg = <0x400f3c00 0x200>;
|
||||
interrupts = <172 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
emi0: emi@400f4000 {
|
||||
reg = <0x400f4000 0x400>;
|
||||
interrupts = <42 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
emi1: emi@400f4400 {
|
||||
reg = <0x400f4400 0x400>;
|
||||
interrupts = <43 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
emi2: emi@400f4800 {
|
||||
reg = <0x400f4800 0x400>;
|
||||
interrupts = <44 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
/* Capture Host writes to a 4-byte I/O range
|
||||
* plus a one byte alias I/O location which maps
|
||||
* to one of the 4-byte locations.
|
||||
*/
|
||||
p80bd0: p80bd@400f8000 {
|
||||
reg = <0x400f8000 0x400>;
|
||||
interrupts = <62 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
/* eSPI target attached flash controller.
|
||||
* When this device is fully activated via its driver, it takes
|
||||
* ownership of the QSPI controller. EC access to QSPI
|
||||
* registers is discarded by hardware.
|
||||
*/
|
||||
espi_taf0: espi_taf@40008000 {
|
||||
reg = <0x40008000 0x400>, <0x40070000 0x400>, <0x40071000 0x400>;
|
||||
reg-names = "tafbr", "tafqspi", "tafcomm";
|
||||
interrupts = <166 3>, <167 3>;
|
||||
interrupt-names = "done", "err";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
|
||||
&systick {
|
||||
status = "disabled";
|
||||
};
|
||||
18
dts/arm/microchip/mec5/mec5_dma_chan16.dtsi
Normal file
18
dts/arm/microchip/mec5/mec5_dma_chan16.dtsi
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* MEC5 central DMA controller with 16 channels */
|
||||
dmac: dmac@40002400 {
|
||||
reg = <0x40002400 0xc00>;
|
||||
interrupts = <24 1>, <25 1>, <26 1>, <27 1>,
|
||||
<28 1>, <29 1>, <30 1>, <31 1>,
|
||||
<32 1>, <33 1>, <34 1>, <35 1>,
|
||||
<36 1>, <37 1>, <38 1>, <39 1>;
|
||||
#dma-cells = <2>;
|
||||
dma-channels = <16>;
|
||||
dma-requests = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
19
dts/arm/microchip/mec5/mec5_dma_chan20.dtsi
Normal file
19
dts/arm/microchip/mec5/mec5_dma_chan20.dtsi
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* MEC5 central DMA controller with 20 channels */
|
||||
dmac: dmac@40002400 {
|
||||
reg = <0x40002400 0xc00>;
|
||||
interrupts = <24 1>, <25 1>, <26 1>, <27 1>,
|
||||
<28 1>, <29 1>, <30 1>, <31 1>,
|
||||
<32 1>, <33 1>, <34 1>, <35 1>,
|
||||
<36 1>, <37 1>, <38 1>, <39 1>,
|
||||
<194 1>, <195 1>, <196 1>, <197 1>;
|
||||
#dma-cells = <2>;
|
||||
dma-channels = <20>;
|
||||
dma-requests = <20>;
|
||||
status = "disabled";
|
||||
};
|
||||
13
dts/arm/microchip/mec5/mec5_eeprom_8kb.dtsi
Normal file
13
dts/arm/microchip/mec5/mec5_eeprom_8kb.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* MEC5 EEPROM controller with internal 8 kilobyte EEPROM */
|
||||
eeprom: eeprom@40002c00 {
|
||||
reg = <0x40002c00 0x400>;
|
||||
interrupts = <155 2>;
|
||||
size = <8192>;
|
||||
status = "disabled";
|
||||
};
|
||||
19
dts/arm/microchip/mec5/mec5_gpspi_v1.dtsi
Normal file
19
dts/arm/microchip/mec5/mec5_gpspi_v1.dtsi
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* Microchip MEC5 MEC172x and MEC5200 GP-SPI controller version 1 hardware
|
||||
* Include this file in the soc {} section in the above chip DTSI files.
|
||||
*/
|
||||
gpspi0: spi@40009400 {
|
||||
reg = <0x40009400 0x80>;
|
||||
interrupts = <92 2>, <93 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
gpspi1: spi@40009480 {
|
||||
reg = <0x40009480 0x80>;
|
||||
interrupts = <94 2>, <95 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
21
dts/arm/microchip/mec5/mec5_gpspi_v2.dtsi
Normal file
21
dts/arm/microchip/mec5/mec5_gpspi_v2.dtsi
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* From Microchip MEC5 MEC174x and onwards use GP-SPI controller version 2 hardware,
|
||||
* a completely different design. Don't ask why it was given the same name;<)
|
||||
* Include this file in the soc {} section in the relevant chip DTSI files
|
||||
*/
|
||||
gpspi0: spi@40009400 {
|
||||
reg = <0x40009400 0x80>;
|
||||
interrupts = <92 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpspi1: spi@40009480 {
|
||||
reg = <0x40009480 0x80>;
|
||||
interrupts = <94 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
25
dts/arm/microchip/mec5/mec5_pkg176_pwms.dtsi
Normal file
25
dts/arm/microchip/mec5/mec5_pkg176_pwms.dtsi
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* So far all Microchip MEC5 family of SoC's so add three more PWM's
|
||||
* in the 176-pin (LJ) package.
|
||||
* Include this file in the soc {} section in all MEC5 LJ chip DTSI files.
|
||||
*/
|
||||
pwm9: pwm@40005890 {
|
||||
reg = <0x40005890 0x10>;
|
||||
status = "disabled";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
pwm10: pwm@400058a0 {
|
||||
reg = <0x400058a0 0x10>;
|
||||
status = "disabled";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
pwm11: pwm@400058b0 {
|
||||
reg = <0x400058b0 0x10>;
|
||||
status = "disabled";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
25
dts/arm/microchip/mec5/mec5_pkg176_uarts.dtsi
Normal file
25
dts/arm/microchip/mec5/mec5_pkg176_uarts.dtsi
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* Microchip MEC5 MEC174x, MEC540x, MEC175x, and MEC550x add two more UART's
|
||||
* in the 176-pin (LJ) package.
|
||||
* Include this file in the soc {} section in the above chip DTSI files.
|
||||
*/
|
||||
uart2: uart@400f2c00 {
|
||||
reg = <0x400f2c00 0x400>;
|
||||
interrupts = <183 1>;
|
||||
clock-frequency = <1843200>;
|
||||
current-speed = <38400>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: uart@400f3000 {
|
||||
reg = <0x400f3000 0x400>;
|
||||
interrupts = <184 1>;
|
||||
clock-frequency = <1843200>;
|
||||
current-speed = <38400>;
|
||||
status = "disabled";
|
||||
};
|
||||
20
dts/arm/microchip/mec5/mec5_power_guards.dtsi
Normal file
20
dts/arm/microchip/mec5/mec5_power_guards.dtsi
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* Microchip MEC5 SoC's optional hardware power guard controllers
|
||||
* Include this file in the soc {} section in the relevant chip DTSI files.
|
||||
*/
|
||||
pwrgrd0: pwrgrd@40003000 {
|
||||
reg = <0x40003000 0x80>;
|
||||
interrupts = <88 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwrgrd1: pwrgrd@40003080 {
|
||||
reg = <0x40003080 0x80>;
|
||||
interrupts = <89 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
34
dts/arm/microchip/mec5_mec1743qlj.dtsi
Normal file
34
dts/arm/microchip/mec5_mec1743qlj.dtsi
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
|
||||
#include "mec5.dtsi"
|
||||
|
||||
/ {
|
||||
flash0: flash@b0000 {
|
||||
reg = <0x000b0000 0x68000>;
|
||||
};
|
||||
|
||||
sram0: memory@118000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00118000 0xf800>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#include "mec5/mec5_dma_chan16.dtsi"
|
||||
#include "mec5/mec5_gpspi_v2.dtsi"
|
||||
#include "mec5/mec5_eeprom_8kb.dtsi"
|
||||
#include "mec5/mec5_pkg176_pwms.dtsi"
|
||||
#include "mec5/mec5_pkg176_uarts.dtsi"
|
||||
|
||||
kscan0: kscan@40009c00 {
|
||||
reg = <0x40009c00 0x18>;
|
||||
interrupts = <135 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
40
dts/arm/microchip/mec5_mec1743qsz.dtsi
Normal file
40
dts/arm/microchip/mec5_mec1743qsz.dtsi
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
|
||||
#include "mec5.dtsi"
|
||||
|
||||
/ {
|
||||
flash0: flash@b0000 {
|
||||
reg = <0x000b0000 0x68000>;
|
||||
};
|
||||
|
||||
sram0: memory@118000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00118000 0xf800>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#include "mec5/mec5_dma_chan16.dtsi"
|
||||
#include "mec5/mec5_gpspi_v2.dtsi"
|
||||
#include "mec5/mec5_eeprom_8kb.dtsi"
|
||||
|
||||
kscan0: kscan@40009c00 {
|
||||
reg = <0x40009c00 0x18>;
|
||||
interrupts = <135 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: uart@400f2c00 {
|
||||
reg = <0x400f2c00 0x400>;
|
||||
interrupts = <183 1>;
|
||||
clock-frequency = <1843200>;
|
||||
current-speed = <38400>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
36
dts/arm/microchip/mec5_mec1753qlj.dtsi
Normal file
36
dts/arm/microchip/mec5_mec1753qlj.dtsi
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
|
||||
#include "mec5.dtsi"
|
||||
|
||||
/ {
|
||||
flash0: flash@b0000 {
|
||||
reg = <0x000b0000 0x68000>;
|
||||
};
|
||||
|
||||
sram0: memory@118000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00118000 0xf800>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#include "mec5/mec5_dma_chan20.dtsi"
|
||||
#include "mec5/mec5_eeprom_8kb.dtsi"
|
||||
#include "mec5/mec5_gpspi_v2.dtsi"
|
||||
#include "mec5/mec5_pkg176_pwms.dtsi"
|
||||
#include "mec5/mec5_pkg176_uarts.dtsi"
|
||||
#include "mec5/mec5_i3c.dtsi"
|
||||
|
||||
kscan0: kscan@40009c00 {
|
||||
reg = <0x40009c00 0x18>;
|
||||
interrupts = <135 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
42
dts/arm/microchip/mec5_mec1753qsz.dtsi
Normal file
42
dts/arm/microchip/mec5_mec1753qsz.dtsi
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
|
||||
#include "mec5.dtsi"
|
||||
#include "mec5/mec5_mec175xsz-espi-host-dev.dtsi"
|
||||
|
||||
/ {
|
||||
flash0: flash@b0000 {
|
||||
reg = <0x000b0000 0x68000>;
|
||||
};
|
||||
|
||||
sram0: memory@118000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00118000 0xf800>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#include "mec5/mec5_dma_chan20.dtsi"
|
||||
#include "mec5/mec5_eeprom_8kb.dtsi"
|
||||
#include "mec5/mec5_gpspi_v2.dtsi"
|
||||
#include "mec5/mec5_i3c.dtsi"
|
||||
|
||||
kscan0: kscan@40009c00 {
|
||||
reg = <0x40009c00 0x18>;
|
||||
interrupts = <135 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: uart@400f2c00 {
|
||||
reg = <0x400f2c00 0x400>;
|
||||
interrupts = <183 1>;
|
||||
clock-frequency = <1843200>;
|
||||
current-speed = <38400>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
33
dts/arm/microchip/mec5_mech1723nlj.dtsi
Normal file
33
dts/arm/microchip/mec5_mech1723nlj.dtsi
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
|
||||
#include "mec5.dtsi"
|
||||
|
||||
/ {
|
||||
flash0: flash@c0000 {
|
||||
reg = <0x000c0000 0x58000>;
|
||||
};
|
||||
|
||||
sram0: memory@118000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00118000 0xf800>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#include "mec5/mec5_dma_chan16.dtsi"
|
||||
#include "mec5/mec5_gpspi_v1.dtsi"
|
||||
#include "mec5/mec5_eeprom_8kb.dtsi"
|
||||
#include "mec5/mec5_pkg176_pwms.dtsi"
|
||||
|
||||
kscan0: kscan@40009c00 {
|
||||
reg = <0x40009c00 0x18>;
|
||||
interrupts = <135 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
32
dts/arm/microchip/mec5_mech1723nsz.dtsi
Normal file
32
dts/arm/microchip/mec5_mech1723nsz.dtsi
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Microchip Technology Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
|
||||
#include "mec5.dtsi"
|
||||
|
||||
/ {
|
||||
flash0: flash@c0000 {
|
||||
reg = <0x000c0000 0x58000>;
|
||||
};
|
||||
|
||||
sram0: memory@118000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00118000 0xf800>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#include "mec5/mec5_dma_chan16.dtsi"
|
||||
#include "mec5/mec5_gpspi_v1.dtsi"
|
||||
#include "mec5/mec5_eeprom_8kb.dtsi"
|
||||
|
||||
kscan0: kscan@40009c00 {
|
||||
reg = <0x40009c00 0x18>;
|
||||
interrupts = <135 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in a new issue