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dts: stm32h5: Add SDMMC nodes

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Add sdmmc1 and sdmmc2 nodes descriptions for STM32H5 SoCs.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
This commit is contained in:
Erwan Gouriou 2024-04-04 10:58:35 +02:00 committed by Fabio Baltieri
parent 629bfd9f9f
commit a6f94f65a0
2 changed files with 20 additions and 0 deletions
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10
dts/arm/st/h5/stm32h562.dtsi
View file

@ -376,6 +376,16 @@
bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>; bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
status = "disabled"; status = "disabled";
}; };
sdmmc1: sdmmc@46008000 {
compatible = "st,stm32-sdmmc";
reg = <0x46008000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000800>,
<&rcc STM32_SRC_PLL1_Q SDMMC1_SEL(0)>;
resets = <&rctl STM32_RESET(AHB4, 11U)>;
interrupts = <79 0>;
status = "disabled";
};
}; };
smbus3: smbus3 { smbus3: smbus3 {

10
dts/arm/st/h5/stm32h563.dtsi
View file

@ -9,5 +9,15 @@
/ { / {
soc { soc {
compatible = "st,stm32h563", "st,stm32h5", "simple-bus"; compatible = "st,stm32h563", "st,stm32h5", "simple-bus";
sdmmc2: sdmmc@46008c00 {
compatible = "st,stm32-sdmmc";
reg = <0x46008c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00001000>,
<&rcc STM32_SRC_PLL1_Q SDMMC2_SEL(0)>;
resets = <&rctl STM32_RESET(AHB4, 12U)>;
interrupts = <102 0>;
status = "disabled";
};
}; };
}; };