adafruit-mirror/zephyr
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions 8

drivers: interrupt_controller: nuclei_eclic: always use clic common entry

Browse source 
When CONFIG_RISCV_VECTORED_MODE is disabled, CLIC claims interrupts using
CSR 'mnxti' and handles all pending interrupts before exiting the ISR.

When CONFIG_RISCV_VECTORED_MODE is enabled, all interrupts use vector mode
and are claimed automatically. The RISC-V common ISR is used for interrupts
hooked into SW ISR table, but it only handle one pending interrupt per ISR.

This commit enhances CLIC to set vector mode for direct ISRs only and use
the CLIC common entry for regular ISRs to handles multiple pending
interrupts in an ISR.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng 2024-08-05 11:17:39 +08:00 committed by Carles Cufí
parent d55950c23f
commit a7096fac7d
3 changed files with 9 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/interrupt_controller/Kconfig.clic
View file

@ -5,7 +5,7 @@ config NUCLEI_ECLIC
bool "Enhanced Core Local Interrupt Controller (ECLIC)"
default y
depends on DT_HAS_NUCLEI_ECLIC_ENABLED
select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING if !RISCV_VECTORED_MODE
select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
select CLIC_SMCLICSHV_EXT if RISCV_VECTORED_MODE
help
Interrupt controller for Nuclei SoC core.

14
drivers/interrupt_controller/intc_nuclei_eclic.S
View file

@ -22,8 +22,6 @@ GTEXT(__soc_handle_irq)
SECTION_FUNC(exception.other, __soc_handle_irq)
ret
#if !defined(CONFIG_RISCV_VECTORED_MODE)
GTEXT(__soc_handle_all_irqs)
#ifdef CONFIG_TRACING
@ -50,8 +48,10 @@ irq_loop:
call sys_trace_isr_enter
#endif
/* Call corresponding registered function in _sw_isr_table. a0 is offset in words, table is
* 2-word wide -> shift by one */
/* Call corresponding registered function in _sw_isr_table. a0 is offset in pointer with
* the mtvt, sw irq table is 2-pointer wide -> shift by one. */
csrr t0, 0x307 /* mtvt */
sub a0, a0, t0
la t0, _sw_isr_table
slli a0, a0, (1)
add t0, t0, a0
@ -65,17 +65,15 @@ irq_loop:
/* Call ISR function */
jalr ra, t1, 0
/* Read and clear mnxti to get highest current interrupt and enable interrupts. */
csrrci a0, 0x345, MSTATUS_IEN
#ifdef CONFIG_TRACING_ISR
call sys_trace_isr_exit
#endif
/* Read and clear mnxti to get highest current interrupt and enable interrupts. */
csrrci a0, 0x345, MSTATUS_IEN
bnez a0, irq_loop
irq_done:
lw ra, 0(sp)
addi sp, sp, 16
ret
#endif

11
drivers/interrupt_controller/intc_nuclei_eclic.c
View file

@ -144,16 +144,9 @@ void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)
ECLIC_CTRL[irq].INTCTRL = intctrl;
union CLICINTATTR intattr = {.w = 0};
#if defined(CONFIG_RISCV_VECTORED_MODE) && !defined(CONFIG_LEGACY_CLIC)
/*
* Set Selective Hardware Vectoring.
* Legacy SiFive does not implement smclicshv extension and vectoring is
* enabled in the mode bits of mtvec.
*/
intattr.b.shv = 1;
#else
/* Set non-vectoring as default. */
intattr.b.shv = 0;
#endif
intattr.b.trg = (uint8_t)(flags & CLIC_INTATTR_TRIG_Msk);
ECLIC_CTRL[irq].INTATTR = intattr;
}