dts: add the ch32v003 dtsi

This commit adds the dtsi and bindings for the WCH CH32V003 which is a
32-bit general-purpose RISC-V MCU.

Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>

dts/bindings/cpu/wch,qingke-v2.yaml

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Dhiru Kholia <dhiru.kholia@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: WCH QingKe V2 RISC-V MCU
+
+compatible: "wch,qingke-v2"
+
+include: cpu.yaml

dts/bindings/vendor-prefixes.txt

@@ -723,6 +723,7 @@ vot	Vision Optical Technology Co., Ltd.
 vxt	VXT Ltd
 wand	Wandbord (Technexion)
 waveshare	Waveshare Electronics
+wch	WinChipHead
 wd	Western Digital Corp.
 we	Würth Elektronik GmbH.
 weact	WeAct Studio

dts/riscv/wch/ch32v00x.dtsi

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/clock/ch32v00x-clocks.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "wch,qingke-v2";
+			reg = <0>;
+			clock-frequency = <DT_FREQ_M(48)>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 0x800>;
+		};
+
+		flash: flash-controller@40022000 {
+			compatible = "wch,ch32v00x-flash-controller";
+			reg = <0x40022000 0x400>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0 0x4000>;
+			};
+		};
+
+		pfic: interrupt-controller@e000e000 {
+			compatible = "wch,pfic";
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0xe000e000 16>;
+			status = "okay";
+		};
+
+		systick: systimer@e000f000 {
+			compatible = "wch,systick";
+			reg = <0xe000f000 16>;
+			status = "okay";
+			interrupt-parent = <&pfic>;
+			interrupts = <12>;
+		};
+
+		pwr: pwr@40007000 {
+			compatible = "wch,pwr";
+			reg = <0x40007000 16>;
+		};
+
+		pinctrl: pin-controller@40010000 {
+			compatible = "wch,afio";
+			reg = <0x40010000 16>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "okay";
+
+			gpioa: gpio@40010800 {
+				compatible = "wch,gpio";
+				reg = <0x40010800 32>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				clocks = <&rcc CH32V00X_CLOCK_IOPA>;
+			};
+
+			gpioc: gpio@40011000 {
+				compatible = "wch,gpio";
+				reg = <0x40011000 32>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				clocks = <&rcc CH32V00X_CLOCK_IOPC>;
+			};
+
+			gpiod: gpio@40011400 {
+				compatible = "wch,gpio";
+				reg = <0x40011400 32>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				clocks = <&rcc CH32V00X_CLOCK_IOPD>;
+			};
+		};
+
+		usart1: uart@40013800 {
+			compatible = "wch,usart";
+			reg = <0x40013800 16>;
+			clocks = <&rcc CH32V00X_CLOCK_USART1>;
+			interrupt-parent = <&pfic>;
+			interrupts = <32>;
+		};
+
+		rcc: rcc@40021000 {
+			compatible = "wch,rcc";
+			reg = <0x40021000 16>;
+			#clock-cells = <1>;
+			status = "okay";
+		};
+	};
+};