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driver: pwm: infineon: cyw920829m2evk_02 pwm

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- Enable PWM for the cyw920829m2evk_02 board

Signed-off-by: Bill Waters <bill.waters@infineon.com>
This commit is contained in:
Bill Waters 2024-09-26 07:24:06 -07:00 committed by David Leach
parent 5e3fe2765a
commit abca729367
15 changed files with 649 additions and 4 deletions
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2
boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml
View file

@ -21,5 +21,7 @@ supported:
- spi
- i2c
- rtc
- dma
- pwm
vendor: infineon

1
drivers/pwm/CMakeLists.txt
View file

@ -45,6 +45,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_NXP_FLEXIO pwm_nxp_flexio.c)
zephyr_library_sources_ifdef(CONFIG_PWM_NXP_S32_EMIOS pwm_nxp_s32_emios.c)
zephyr_library_sources_ifdef(CONFIG_PWM_ENE_KB1200 pwm_ene_kb1200.c)
zephyr_library_sources_ifdef(CONFIG_PWM_RENESAS_RA8 pwm_renesas_ra8.c)
zephyr_library_sources_ifdef(CONFIG_PWM_INFINEON_CAT1 pwm_ifx_cat1.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE pwm_handlers.c)
zephyr_library_sources_ifdef(CONFIG_PWM_CAPTURE pwm_capture.c)

2
drivers/pwm/Kconfig
View file

@ -110,4 +110,6 @@ source "drivers/pwm/Kconfig.ene"
source "drivers/pwm/Kconfig.renesas_ra8"
source "drivers/pwm/Kconfig.ifx_cat1"
endif # PWM

16
drivers/pwm/Kconfig.ifx_cat1 Normal file
View file

@ -0,0 +1,16 @@
# Infineon CAT1 PWM configuration options
# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
#
# SPDX-License-Identifier: Apache-2.0
config PWM_INFINEON_CAT1
bool "Infineon CAT1 PWM driver"
default y
depends on DT_HAS_INFINEON_CAT1_PWM_ENABLED
depends on SOC_FAMILY_INFINEON_CAT1B
select USE_INFINEON_PWM
select PINCTRL
help
This option enables the PWM driver for Infineon CAT1 family.

177
drivers/pwm/pwm_ifx_cat1.c Normal file
View file

@ -0,0 +1,177 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief ADC driver for Infineon CAT1 MCU family.
*/
#define DT_DRV_COMPAT infineon_cat1_pwm
#include <zephyr/drivers/pwm.h>
#include <zephyr/drivers/pinctrl.h>
#include <cy_tcpwm_pwm.h>
#include <cy_gpio.h>
#include <cy_sysclk.h>
#include <cyhal_hw_resources.h>
#include <cyhal_hw_types.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pwm_ifx_cat1, CONFIG_PWM_LOG_LEVEL);
#define PWM_REG_BASE TCPWM0
struct ifx_cat1_pwm_data {
uint32_t pwm_num;
};
struct ifx_cat1_pwm_config {
TCPWM_GRP_CNT_Type *reg_addr;
const struct pinctrl_dev_config *pcfg;
bool resolution_32_bits;
cy_en_divider_types_t divider_type;
uint32_t divider_sel;
uint32_t divider_val;
};
static int ifx_cat1_pwm_init(const struct device *dev)
{
struct ifx_cat1_pwm_data *data = dev->data;
const struct ifx_cat1_pwm_config *config = dev->config;
cy_en_tcpwm_status_t status;
int ret;
uint32_t addr_offset = (uint32_t)config->reg_addr - TCPWM0_BASE;
uint32_t clk_connection;
const cy_stc_tcpwm_pwm_config_t pwm_config = {
.pwmMode = CY_TCPWM_PWM_MODE_PWM,
.clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1,
.pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN,
.runMode = CY_TCPWM_PWM_CONTINUOUS,
.countInputMode = CY_TCPWM_INPUT_LEVEL,
.countInput = CY_TCPWM_INPUT_1,
};
/* Configure PWM clock */
Cy_SysClk_PeriphDisableDivider(config->divider_type, config->divider_sel);
Cy_SysClk_PeriphSetDivider(config->divider_type, config->divider_sel, config->divider_val);
Cy_SysClk_PeriphEnableDivider(config->divider_type, config->divider_sel);
/* This is very specific to the cyw920829m2evk_02 and may need to be modified
* for other boards.
*/
if (addr_offset < sizeof(TCPWM_GRP_Type)) {
clk_connection =
PCLK_TCPWM0_CLOCK_COUNTER_EN0 + (addr_offset / sizeof(TCPWM_GRP_CNT_Type));
} else {
addr_offset -= sizeof(TCPWM_GRP_Type);
clk_connection = PCLK_TCPWM0_CLOCK_COUNTER_EN256 +
(addr_offset / sizeof(TCPWM_GRP_CNT_Type));
}
Cy_SysClk_PeriphAssignDivider(clk_connection, config->divider_type, config->divider_sel);
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
/* Configure the TCPWM to be a PWM */
data->pwm_num += addr_offset / sizeof(TCPWM_GRP_CNT_Type);
status = Cy_TCPWM_PWM_Init(PWM_REG_BASE, data->pwm_num, &pwm_config);
if (status != CY_TCPWM_SUCCESS) {
return -ENOTSUP;
}
return 0;
}
static int ifx_cat1_pwm_set_cycles(const struct device *dev, uint32_t channel,
uint32_t period_cycles, uint32_t pulse_cycles, pwm_flags_t flags)
{
struct ifx_cat1_pwm_data *data = dev->data;
const struct ifx_cat1_pwm_config *config = dev->config;
if (!config->resolution_32_bits &&
((period_cycles > UINT16_MAX) || (pulse_cycles > UINT16_MAX))) {
/* 16-bit resolution */
if (period_cycles > UINT16_MAX) {
LOG_ERR("Period cycles more than 16-bits (%u)", period_cycles);
}
if (pulse_cycles > UINT16_MAX) {
LOG_ERR("Pulse cycles more than 16-bits (%u)", pulse_cycles);
}
return -EINVAL;
}
if ((period_cycles == 0) || (pulse_cycles == 0)) {
Cy_TCPWM_PWM_Disable(PWM_REG_BASE, data->pwm_num);
} else {
Cy_TCPWM_PWM_SetPeriod0(PWM_REG_BASE, data->pwm_num, period_cycles);
Cy_TCPWM_PWM_SetCompare0Val(PWM_REG_BASE, data->pwm_num, pulse_cycles);
if ((flags & PWM_POLARITY_MASK) == PWM_POLARITY_INVERTED) {
config->reg_addr->CTRL &= ~TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk;
config->reg_addr->CTRL |= _VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE,
CY_TCPWM_PWM_INVERT_ENABLE);
}
/* TODO: Add 2-bit field to top 8 bits of pwm_flags_t to set this.
* #define CY_TCPWM_PWM_OUTPUT_HIGHZ (0U)
* #define CY_TCPWM_PWM_OUTPUT_RETAIN (1U)
* #define CY_TCPWM_PWM_OUTPUT_LOW (2U)
* #define CY_TCPWM_PWM_OUTPUT_HIGH (3U)
* if ((flags & __) == __) {
* config->reg_addr->CTRL &= ~TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk;
* config->reg_addr->CTRL |= _VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE,
* __);
* }
*/
/* Enable the TCPWM for PWM mode of operation */
Cy_TCPWM_PWM_Enable(PWM_REG_BASE, data->pwm_num);
/* Start the TCPWM block */
Cy_TCPWM_TriggerStart_Single(PWM_REG_BASE, data->pwm_num);
}
return 0;
}
static int ifx_cat1_pwm_get_cycles_per_sec(const struct device *dev, uint32_t channel,
uint64_t *cycles)
{
const struct ifx_cat1_pwm_config *config = dev->config;
*cycles = Cy_SysClk_PeriphGetFrequency(config->divider_type, config->divider_sel);
return 0;
}
static const struct pwm_driver_api ifx_cat1_pwm_api = {
.set_cycles = ifx_cat1_pwm_set_cycles,
.get_cycles_per_sec = ifx_cat1_pwm_get_cycles_per_sec,
};
#define INFINEON_CAT1_PWM_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
\
static struct ifx_cat1_pwm_data pwm_cat1_data_##n; \
\
static struct ifx_cat1_pwm_config pwm_cat1_config_##n = { \
.reg_addr = (TCPWM_GRP_CNT_Type *)DT_INST_REG_ADDR(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.resolution_32_bits = (DT_INST_PROP(n, resolution) == 32) ? true : false, \
.divider_type = DT_INST_PROP(n, divider_type), \
.divider_sel = DT_INST_PROP(n, divider_sel), \
.divider_val = DT_INST_PROP(n, divider_val), \
}; \
\
DEVICE_DT_INST_DEFINE(n, ifx_cat1_pwm_init, NULL, &pwm_cat1_data_##n, \
&pwm_cat1_config_##n, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
&ifx_cat1_pwm_api);
DT_INST_FOREACH_STATUS_OKAY(INFINEON_CAT1_PWM_INIT)

105
dts/arm/infineon/cat1b/cyw20829/cyw20829.40-qfn.dtsi
View file

@ -188,6 +188,111 @@
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_6)>;
};
/* PWM group 0 */
/omit-if-no-ref/ p0_1_pwm0_1: p0_1_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p0_3_pwm0_0: p0_3_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p0_5_pwm0_1: p0_5_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p1_1_pwm0_0: p1_1_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p1_3_pwm0_1: p1_3_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p1_5_pwm0_0: p1_5_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p3_0_pwm0_0: p3_0_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p3_2_pwm0_1: p3_2_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p3_4_pwm0_0: p3_4_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p3_6_pwm0_1: p3_6_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p4_1_pwm0_0: p4_1_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p5_0_pwm0_0: p5_0_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p5_2_pwm0_1: p5_2_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_0)>;
};
/* PWM group 1 */
/omit-if-no-ref/ p0_1_pwm1_0: p0_1_pwm1_0 {
pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p0_3_pwm1_1: p0_3_pwm1_1 {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p0_5_pwm1_2: p0_5_pwm1_2 {
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p1_1_pwm1_3: p1_1_pwm1_3 {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p1_3_pwm1_4: p1_3_pwm1_4 {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p1_5_pwm1_5: p1_5_pwm1_5 {
pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p3_0_pwm1_0: p3_0_pwm1_0 {
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p3_2_pwm1_1: p3_2_pwm1_1 {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p3_4_pwm1_2: p3_4_pwm1_2 {
pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p3_6_pwm1_3: p3_6_pwm1_3 {
pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p4_1_pwm1_6: p4_1_pwm1_6 {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p5_0_pwm1_4: p5_0_pwm1_4 {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p5_2_pwm1_5: p5_2_pwm1_5 {
pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_1)>;
};
};
};
};

106
dts/arm/infineon/cat1b/cyw20829/cyw20829.56-qfn.dtsi
View file

@ -10,7 +10,6 @@
#include "cyw20829.dtsi"
/ {
soc {
pinctrl: pinctrl@40400000 {
@ -252,6 +251,111 @@
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_6)>;
};
/* PWM group 0 */
/omit-if-no-ref/ p0_1_pwm0_1: p0_1_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p0_3_pwm0_0: p0_3_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p0_5_pwm0_1: p0_5_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p1_1_pwm0_0: p1_1_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p1_3_pwm0_1: p1_3_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p1_5_pwm0_0: p1_5_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p3_0_pwm0_0: p3_0_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p3_2_pwm0_1: p3_2_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p3_4_pwm0_0: p3_4_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p3_6_pwm0_1: p3_6_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p4_1_pwm0_0: p4_1_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p5_0_pwm0_0: p5_0_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p5_2_pwm0_1: p5_2_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_0)>;
};
/* PWM group 1 */
/omit-if-no-ref/ p0_1_pwm1_0: p0_1_pwm1_0 {
pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p0_3_pwm1_1: p0_3_pwm1_1 {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p0_5_pwm1_2: p0_5_pwm1_2 {
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p1_1_pwm1_3: p1_1_pwm1_3 {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p1_3_pwm1_4: p1_3_pwm1_4 {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p1_5_pwm1_5: p1_5_pwm1_5 {
pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p3_0_pwm1_0: p3_0_pwm1_0 {
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p3_2_pwm1_1: p3_2_pwm1_1 {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p3_4_pwm1_2: p3_4_pwm1_2 {
pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p3_6_pwm1_3: p3_6_pwm1_3 {
pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p4_1_pwm1_6: p4_1_pwm1_6 {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p5_0_pwm1_4: p5_0_pwm1_4 {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p5_2_pwm1_5: p5_2_pwm1_5 {
pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_1)>;
};
};
};
};

105
dts/arm/infineon/cat1b/cyw20829/cyw20829.77-bga.dtsi
View file

@ -251,6 +251,111 @@
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_6)>;
};
/* PWM group 0 */
/omit-if-no-ref/ p0_1_pwm0_1: p0_1_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p0_3_pwm0_0: p0_3_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p0_5_pwm0_1: p0_5_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p1_1_pwm0_0: p1_1_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p1_3_pwm0_1: p1_3_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p1_5_pwm0_0: p1_5_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p3_0_pwm0_0: p3_0_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p3_2_pwm0_1: p3_2_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p3_4_pwm0_0: p3_4_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p3_6_pwm0_1: p3_6_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p4_1_pwm0_0: p4_1_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p5_0_pwm0_0: p5_0_pwm0_0 {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_0)>;
};
/omit-if-no-ref/ p5_2_pwm0_1: p5_2_pwm0_1 {
pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_0)>;
};
/* PWM group 1 */
/omit-if-no-ref/ p0_1_pwm1_0: p0_1_pwm1_0 {
pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p0_3_pwm1_1: p0_3_pwm1_1 {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p0_5_pwm1_2: p0_5_pwm1_2 {
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p1_1_pwm1_3: p1_1_pwm1_3 {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p1_3_pwm1_4: p1_3_pwm1_4 {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p1_5_pwm1_5: p1_5_pwm1_5 {
pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p3_0_pwm1_0: p3_0_pwm1_0 {
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p3_2_pwm1_1: p3_2_pwm1_1 {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p3_4_pwm1_2: p3_4_pwm1_2 {
pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p3_6_pwm1_3: p3_6_pwm1_3 {
pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p4_1_pwm1_6: p4_1_pwm1_6 {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p5_0_pwm1_4: p5_0_pwm1_4 {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_1)>;
};
/omit-if-no-ref/ p5_2_pwm1_5: p5_2_pwm1_5 {
pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_1)>;
};
};
};
};

9
dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi
View file

@ -216,6 +216,7 @@
interrupts = <42 4>;
resolution = <32>;
status = "disabled";
#pwm-cells = <3>;
};
pwm0_1: pwm@404a0080 {
compatible = "infineon,cat1-pwm";
@ -223,6 +224,7 @@
interrupts = <43 4>;
resolution = <32>;
status = "disabled";
#pwm-cells = <3>;
};
pwm1_0: pwm@404a8000 {
compatible = "infineon,cat1-pwm";
@ -230,6 +232,7 @@
interrupts = <44 4>;
resolution = <16>;
status = "disabled";
#pwm-cells = <3>;
};
pwm1_1: pwm@404a8080 {
compatible = "infineon,cat1-pwm";
@ -237,6 +240,7 @@
interrupts = <45 4>;
resolution = <16>;
status = "disabled";
#pwm-cells = <3>;
};
pwm1_2: pwm@404a8100 {
compatible = "infineon,cat1-pwm";
@ -244,6 +248,7 @@
interrupts = <46 4>;
resolution = <16>;
status = "disabled";
#pwm-cells = <3>;
};
pwm1_3: pwm@404a8180 {
compatible = "infineon,cat1-pwm";
@ -251,6 +256,7 @@
interrupts = <47 4>;
resolution = <16>;
status = "disabled";
#pwm-cells = <3>;
};
pwm1_4: pwm@404a8200 {
compatible = "infineon,cat1-pwm";
@ -258,6 +264,7 @@
interrupts = <48 4>;
resolution = <16>;
status = "disabled";
#pwm-cells = <3>;
};
pwm1_5: pwm@404a8280 {
compatible = "infineon,cat1-pwm";
@ -265,6 +272,7 @@
interrupts = <49 4>;
resolution = <16>;
status = "disabled";
#pwm-cells = <3>;
};
pwm1_6: pwm@404a8300 {
compatible = "infineon,cat1-pwm";
@ -272,6 +280,7 @@
interrupts = <50 4>;
resolution = <16>;
status = "disabled";
#pwm-cells = <3>;
};
dma0: dw@40180000 {

70
dts/bindings/pwm/infineon,cat1-pwm.yaml Normal file
View file

@ -0,0 +1,70 @@
# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
#
# SPDX-License-Identifier: Apache-2.0
description: Infineon Cat1 PWM
compatible: "infineon,cat1-pwm"
include: [pwm-controller.yaml, pinctrl-device.yaml]
properties:
reg:
type: array
required: true
interrupts:
type: array
required: true
pinctrl-0:
description: |
PORT pin configuration for the PWM signal.
We expect that the phandles will reference pinctrl nodes. These
nodes will have a nodelabel that matches the Infineon SoC Pinctrl
defines and have following
format: p<port>_<pin>_<peripheral inst>_<signal>.
Examples:
pinctrl-0 = <&p1_1_pwm0_0>;
required: true
pinctrl-names:
required: true
resolution:
type: int
divider-type:
type: int
description: |
Specifies which type of divider to use.
Defined by cy_en_divider_types_t in cy_sysclk.h.
required: true
divider-sel:
type: int
description: |
Specifies which divider of the selected type to configure.
required: true
divider-val:
type: int
description: |
Causes integer division of (divider value + 1), or division by 1 to 256
(8-bit divider) or 1 to 65536 (16-bit divider).
required: true
"#pwm-cells":
const: 3
description: |
Number of items to expect in a PWM
- channel of the timer used for PWM (not used)
- period to set in ns
- flags: standard flags like PWM_POLARITY_NORMAL
pwm-cells:
- channel
- period
- flags

11
include/zephyr/dt-bindings/pwm/pwm_ifx_cat1.h Normal file
View file

@ -0,0 +1,11 @@
/* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* Divider Type
*/
#define CY_SYSCLK_DIV_8_BIT 0
#define CY_SYSCLK_DIV_16_BIT 1

3
modules/hal_infineon/Kconfig
View file

@ -66,8 +66,7 @@ config USE_INFINEON_UART
config USE_INFINEON_PWM
bool
help
Enable Pulse Width Modulator (PWM) HAL module
driver for Infineon devices
Enable Pulse Width Modulator (PWM) HAL module driver for Infineon devices
config USE_INFINEON_WDT
bool

1
modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt
View file

@ -78,7 +78,6 @@ zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC ${hal_dir}/source/cyhal
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_FLASH ${hal_dir}/source/cyhal_nvm.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_I2C ${hal_dir}/source/cyhal_i2c.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_LPTIMER ${hal_dir}/source/cyhal_lptimer.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_PWM ${hal_dir}/source/cyhal_pwm.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_RTC ${hal_dir}/source/cyhal_rtc.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SDIO ${hal_dir}/source/cyhal_sdhc.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SPI ${hal_dir}/source/cyhal_spi.c)

6
modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt
View file

@ -45,6 +45,12 @@ zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_UART ${pdl_drv_dir}/source/
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_FLASH ${pdl_drv_dir}/source/cy_flash.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_WDT ${pdl_drv_dir}/source/cy_wdt.c)
if(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC ${pdl_drv_dir}/source/cy_adcmic.c)
else()
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC ${pdl_drv_dir}/source/cy_sar.c)
endif()
if(CONFIG_USE_INFINEON_TRNG)
zephyr_library_sources(${pdl_drv_dir}/source/cy_crypto.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_crypto_core_trng_v1.c)

39
samples/basic/fade_led/boards/cyw920829m2evk_02.overlay Normal file
View file

@ -0,0 +1,39 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*/
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/pwm/pwm_ifx_cat1.h>
/ {
aliases {
pwm-led0 = &pwm_led0;
};
pwmleds {
compatible = "pwm-leds";
pwm_led0: pwm_led_0 {
pwms = <&pwm0_0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "PWM MB1";
};
};
};
&pwm0_0 {
status = "okay";
pinctrl-0 = <&p1_1_pwm0_0>;
pinctrl-names = "default";
divider-type = <CY_SYSCLK_DIV_16_BIT>;
divider-sel = <1>;
divider-val = <9599>;
};
&pinctrl {
p1_1_pwm0_0: p1_1_pwm0_0 {
drive-push-pull;
};
};