drivers: flash: stm32 xspi driver with DMA support
Add the commands to read and write to/from the xSPI with gpDMA On the stm32h5 device, the one request for xspi instance Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu
Anas Nashif
parent
be55b2c263
commit
ac48369731
3 changed files with 210 additions and 1 deletions
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@ -3,6 +3,9 @@
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# Copyright (c) 2024 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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DT_STM32_XSPI_1_HAS_DMA := $(dt_nodelabel_has_prop,xspi1,dmas)
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DT_STM32_XSPI_2_HAS_DMA := $(dt_nodelabel_has_prop,xspi2,dmas)
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config FLASH_STM32_XSPI
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bool "STM32 XSPI Flash driver"
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default y
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@ -13,6 +16,11 @@ config FLASH_STM32_XSPI
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select FLASH_JESD216
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select FLASH_PAGE_LAYOUT
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select FLASH_HAS_PAGE_LAYOUT
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select DMA if $(DT_STM32_XSPI_1_HAS_DMA) || $(DT_STM32_XSPI_2_HAS_DMA)
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select USE_STM32_HAL_DMA if $(DT_STM32_XSPI_1_HAS_DMA) || \
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$(DT_STM32_XSPI_2_HAS_DMA)
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select USE_STM32_HAL_DMA_EX if SOC_SERIES_STM32H5X && \
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($(DT_STM32_XSPI_1_HAS_DMA) || \
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$(DT_STM32_XSPI_2_HAS_DMA))
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help
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Enable XSPI-NOR support on the STM32 family of processors.
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@ -44,6 +44,14 @@ LOG_MODULE_REGISTER(flash_stm32_xspi, CONFIG_FLASH_LOG_LEVEL);
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#define STM32_XSPI_DLYB_BYPASSED DT_PROP(STM32_XSPI_NODE, dlyb_bypass)
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#define STM32_XSPI_USE_DMA DT_NODE_HAS_PROP(STM32_XSPI_NODE, dmas)
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#if STM32_XSPI_USE_DMA
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#include <zephyr/drivers/dma/dma_stm32.h>
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#include <zephyr/drivers/dma.h>
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#include <stm32_ll_dma.h>
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#endif /* STM32_XSPI_USE_DMA */
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#include "flash_stm32_xspi.h"
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static inline void xspi_lock_thread(const struct device *dev)
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@ -97,7 +105,11 @@ static int xspi_read_access(const struct device *dev, XSPI_RegularCmdTypeDef *cm
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return -EIO;
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}
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#if STM32_XSPI_USE_DMA
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hal_ret = HAL_XSPI_Receive_DMA(&dev_data->hxspi, data);
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#else
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hal_ret = HAL_XSPI_Receive_IT(&dev_data->hxspi, data);
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#endif
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if (hal_ret != HAL_OK) {
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LOG_ERR("%d: Failed to read data", hal_ret);
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@ -135,7 +147,11 @@ static int xspi_write_access(const struct device *dev, XSPI_RegularCmdTypeDef *c
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return -EIO;
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}
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#if STM32_XSPI_USE_DMA
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hal_ret = HAL_XSPI_Transmit_DMA(&dev_data->hxspi, (uint8_t *)data);
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#else
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hal_ret = HAL_XSPI_Transmit_IT(&dev_data->hxspi, (uint8_t *)data);
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#endif
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if (hal_ret != HAL_OK) {
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LOG_ERR("%d: Failed to write data", hal_ret);
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@ -1220,6 +1236,24 @@ __weak HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
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}
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#endif /* !CONFIG_SOC_SERIES_STM32H7X */
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/* This function is executed in the interrupt context */
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#if STM32_XSPI_USE_DMA
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static void xspi_dma_callback(const struct device *dev, void *arg,
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uint32_t channel, int status)
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{
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DMA_HandleTypeDef *hdma = arg;
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ARG_UNUSED(dev);
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if (status < 0) {
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LOG_ERR("DMA callback error with channel %d.", channel);
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}
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HAL_DMA_IRQHandler(hdma);
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}
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#endif
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/*
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* Transfer Error callback.
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*/
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@ -1707,6 +1741,85 @@ static int spi_nor_process_bfp(const struct device *dev,
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return 0;
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}
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#if STM32_XSPI_USE_DMA
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static int flash_stm32_xspi_dma_init(DMA_HandleTypeDef *hdma, struct stream *dma_stream)
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{
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int ret;
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/*
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* DMA configuration
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* Due to use of XSPI HAL API in current driver,
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* both HAL and Zephyr DMA drivers should be configured.
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* The required configuration for Zephyr DMA driver should only provide
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* the minimum information to inform the DMA slot will be in used and
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* how to route callbacks.
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*/
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if (!device_is_ready(dma_stream->dev)) {
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LOG_ERR("DMA %s device not ready", dma_stream->dev->name);
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return -ENODEV;
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}
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/* Proceed to the minimum Zephyr DMA driver init of the channel */
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dma_stream->cfg.user_data = hdma;
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/* HACK: This field is used to inform driver that it is overridden */
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dma_stream->cfg.linked_channel = STM32_DMA_HAL_OVERRIDE;
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/* Because of the STREAM OFFSET, the DMA channel given here is from 1 - 8 */
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ret = dma_config(dma_stream->dev,
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(dma_stream->channel + STM32_DMA_STREAM_OFFSET), &dma_stream->cfg);
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if (ret != 0) {
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LOG_ERR("Failed to configure DMA channel %d",
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dma_stream->channel + STM32_DMA_STREAM_OFFSET);
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return ret;
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}
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/* Proceed to the HAL DMA driver init */
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if (dma_stream->cfg.source_data_size != dma_stream->cfg.dest_data_size) {
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LOG_ERR("DMA Source and destination data sizes not aligned");
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return -EINVAL;
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}
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hdma->Init.SrcDataWidth = DMA_SRC_DATAWIDTH_WORD; /* Fixed value */
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hdma->Init.DestDataWidth = DMA_DEST_DATAWIDTH_WORD; /* Fixed value */
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hdma->Init.SrcInc = (dma_stream->src_addr_increment)
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? DMA_SINC_INCREMENTED
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: DMA_SINC_FIXED;
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hdma->Init.DestInc = (dma_stream->dst_addr_increment)
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? DMA_DINC_INCREMENTED
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: DMA_DINC_FIXED;
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hdma->Init.SrcBurstLength = 4;
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hdma->Init.DestBurstLength = 4;
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hdma->Init.Priority = table_priority[dma_stream->cfg.channel_priority];
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hdma->Init.Direction = table_direction[dma_stream->cfg.channel_direction];
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hdma->Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0 | DMA_SRC_ALLOCATED_PORT1;
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hdma->Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
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hdma->Init.Mode = DMA_NORMAL;
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hdma->Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
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hdma->Init.Request = dma_stream->cfg.dma_slot;
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/*
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* HAL expects a valid DMA channel (not DMAMUX).
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* The channel is from 0 to 7 because of the STM32_DMA_STREAM_OFFSET
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* in the dma_stm32 driver
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*/
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hdma->Instance = LL_DMA_GET_CHANNEL_INSTANCE(dma_stream->reg,
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dma_stream->channel);
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/* Initialize DMA HAL */
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if (HAL_DMA_Init(hdma) != HAL_OK) {
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LOG_ERR("XSPI DMA Init failed");
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return -EIO;
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}
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if (HAL_DMA_ConfigChannelAttributes(hdma, DMA_CHANNEL_NPRIV) != HAL_OK) {
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LOG_ERR("XSPI DMA Init failed");
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return -EIO;
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}
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LOG_DBG("XSPI with DMA transfer");
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return 0;
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}
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#endif /* STM32_XSPI_USE_DMA */
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static int flash_stm32_xspi_init(const struct device *dev)
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{
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const struct flash_stm32_xspi_config *dev_cfg = dev->config;
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@ -1859,6 +1972,28 @@ static int flash_stm32_xspi_init(const struct device *dev)
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#endif /* DLYB_ */
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#if STM32_XSPI_USE_DMA
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/* Configure and enable the DMA channels after XSPI config */
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static DMA_HandleTypeDef hdma_tx;
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static DMA_HandleTypeDef hdma_rx;
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if (flash_stm32_xspi_dma_init(&hdma_tx, &dev_data->dma_tx) != 0) {
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LOG_ERR("XSPI DMA Tx init failed");
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return -EIO;
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}
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/* The dma_tx handle is hold by the dma_stream.cfg.user_data */
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__HAL_LINKDMA(&dev_data->hxspi, hdmatx, hdma_tx);
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if (flash_stm32_xspi_dma_init(&hdma_rx, &dev_data->dma_rx) != 0) {
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LOG_ERR("XSPI DMA Rx init failed");
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return -EIO;
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}
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/* The dma_rx handle is hold by the dma_stream.cfg.user_data */
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__HAL_LINKDMA(&dev_data->hxspi, hdmarx, hdma_rx);
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#endif /* CONFIG_USE_STM32_HAL_DMA */
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/* Initialize semaphores */
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k_sem_init(&dev_data->sem, 1, 1);
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k_sem_init(&dev_data->sync, 0, 1);
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@ -2004,6 +2139,39 @@ static int flash_stm32_xspi_init(const struct device *dev)
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return 0;
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}
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#if STM32_XSPI_USE_DMA
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#define DMA_CHANNEL_CONFIG(node, dir) \
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DT_DMAS_CELL_BY_NAME(node, dir, channel_config)
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#define XSPI_DMA_CHANNEL_INIT(node, dir, dir_cap, src_dev, dest_dev) \
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.dev = DEVICE_DT_GET(DT_DMAS_CTLR(node)), \
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.channel = DT_DMAS_CELL_BY_NAME(node, dir, channel), \
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.reg = (DMA_TypeDef *)DT_REG_ADDR( \
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DT_PHANDLE_BY_NAME(node, dmas, dir)), \
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.cfg = { \
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.dma_slot = DT_DMAS_CELL_BY_NAME(node, dir, slot), \
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.channel_direction = STM32_DMA_CONFIG_DIRECTION( \
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DMA_CHANNEL_CONFIG(node, dir)), \
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.channel_priority = STM32_DMA_CONFIG_PRIORITY( \
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DMA_CHANNEL_CONFIG(node, dir)), \
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.dma_callback = xspi_dma_callback, \
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}, \
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.src_addr_increment = STM32_DMA_CONFIG_##src_dev##_ADDR_INC( \
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DMA_CHANNEL_CONFIG(node, dir)), \
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.dst_addr_increment = STM32_DMA_CONFIG_##dest_dev##_ADDR_INC( \
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DMA_CHANNEL_CONFIG(node, dir)),
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#define XSPI_DMA_CHANNEL(node, dir, DIR, src, dest) \
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.dma_##dir = { \
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COND_CODE_1(DT_DMAS_HAS_NAME(node, dir), \
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(XSPI_DMA_CHANNEL_INIT(node, dir, DIR, src, dest)), \
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(NULL)) \
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},
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#else
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#define XSPI_DMA_CHANNEL(node, dir, DIR, src, dest)
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#endif /* CONFIG_USE_STM32_HAL_DMA */
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#define XSPI_FLASH_MODULE(drv_id, flash_id) \
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(DT_DRV_INST(drv_id), xspi_nor_flash_##flash_id)
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@ -2065,6 +2233,8 @@ static struct flash_stm32_xspi_data flash_stm32_xspi_dev_data = {
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), jedec_id)
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.jedec_id = DT_INST_PROP(0, jedec_id),
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#endif /* jedec_id */
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XSPI_DMA_CHANNEL(STM32_XSPI_NODE, tx, TX, MEMORY, PERIPHERAL)
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XSPI_DMA_CHANNEL(STM32_XSPI_NODE, rx, RX, PERIPHERAL, MEMORY)
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};
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static void flash_stm32_xspi_irq_config_func(const struct device *dev)
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@ -37,6 +37,33 @@
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/* used as default value for DTS writeoc */
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#define SPI_NOR_WRITEOC_NONE 0xFF
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#if STM32_XSPI_USE_DMA
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/* Lookup table to set dma priority from the DTS */
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static const uint32_t table_priority[] = {
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DMA_LOW_PRIORITY_LOW_WEIGHT,
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DMA_LOW_PRIORITY_MID_WEIGHT,
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DMA_LOW_PRIORITY_HIGH_WEIGHT,
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DMA_HIGH_PRIORITY,
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};
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/* Lookup table to set dma channel direction from the DTS */
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static const uint32_t table_direction[] = {
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DMA_MEMORY_TO_MEMORY,
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DMA_MEMORY_TO_PERIPH,
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DMA_PERIPH_TO_MEMORY,
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};
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struct stream {
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DMA_TypeDef *reg;
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const struct device *dev;
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uint32_t channel;
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struct dma_config cfg;
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uint8_t priority;
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bool src_addr_increment;
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bool dst_addr_increment;
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};
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#endif /* STM32_XSPI_USE_DMA */
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typedef void (*irq_config_func_t)(const struct device *dev);
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struct flash_stm32_xspi_config {
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@ -77,6 +104,10 @@ struct flash_stm32_xspi_data {
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uint8_t jedec_id[JESD216_READ_ID_LEN];
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#endif /* CONFIG_FLASH_JESD216_API */
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int cmd_status;
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#if STM32_XSPI_USE_DMA
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struct stream dma_tx;
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struct stream dma_rx;
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#endif /* STM32_XSPI_USE_DMA */
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};
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#endif /* ZEPHYR_DRIVERS_FLASH_XSPI_STM32_H_ */
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