boards: riscv: opentitan_earlgrey: Add the OpenTitan AON Timer

Adds the AON Timer device in the OpenTitan Earlgrey device tree.
Adds overlay files to enable the watchdog and set the alias to
`watchdog0`.

Adds the AON timer (watchdog part) to the supported features section
of the OpenTitan documentation.

Signed-off-by: Tyler Ng <tkng@rivosinc.com>

boards/riscv/opentitan_earlgrey/doc/index.rst

@@ -43,6 +43,8 @@ the Earl Grey chip simulated in Verilator, a cycle-accurate HDL simulation tool.
 +-----------+------------+-------------------------------------+
 | SPI       | on-chip    | SPI host                            |
 +-----------+------------+-------------------------------------+
+| WDT       | on-chip    | Always-On Timer (Watchdog)          |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not yet supported on Zephyr porting.
 
@@ -89,8 +91,8 @@ References
 
 .. target-notes::
 
-.. _OpenTitan Earl Grey Chip Datasheet: https://docs.opentitan.org/hw/top_earlgrey/doc/
+.. _OpenTitan Earl Grey Chip Datasheet: https://opentitan.org/book/hw/top_earlgrey/doc/specification.html
 
 .. _OpenTitan GitHub: https://github.com/lowRISC/opentitan
 
-.. _OpenTitan Verilator Setup: https://docs.opentitan.org/doc/getting_started/setup_verilator/
+.. _OpenTitan Verilator Setup: https://opentitan.org/guides/getting_started/setup_verilator.html

boards/riscv/opentitan_earlgrey/opentitan_earlgrey.yaml

@@ -9,3 +9,5 @@ testing:
   ignore_tags:
     - net
     - bluetooth
+supported:
+  - watchdog

dts/riscv/lowrisc/opentitan_earlgrey.dtsi

@@ -53,18 +53,29 @@
 			status = "disabled";
 		};
 
+		aontimer: aontimer@40470000 {
+			compatible = "lowrisc,opentitan-aontimer";
+			reg = <0x40470000 0x1000>;
+			interrupts = <156 1>;
+			interrupt-names = "wdog_bark";
+			interrupt-parent = <&plic>;
+			clock-frequency = <200000>;
+			status = "disabled";
+		};
+
 		plic: interrupt-controller@48000000 {
 			compatible = "sifive,plic-1.0.0";
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 			interrupts-extended = <&hlic 11>;
-			reg = <0x48000000 0x00002000
-			       0x48002000 0x001fe000
-			       0x48000000 0x03e00000>;
+			reg = <0x48000000 0x00001000
+			       0x48002000 0x00001000
+			       0x48200000 0x00000008>;
 			reg-names = "prio", "irq_en", "reg";
 			riscv,max-priority = <7>;
 			riscv,ndev = <184>;
+			status = "okay";
 		};
 
 		uart0: serial@40000000{

samples/drivers/watchdog/boards/opentitan_earlgrey.overlay

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2023 Rivos Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		watchdog0 = &aontimer;
+	};
+};
+
+&aontimer {
+	status = "okay";
+};

tests/drivers/watchdog/wdt_basic_api/boards/opentitan_earlgrey.overlay

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2023 Rivos Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		watchdog0 = &aontimer;
+	};
+};
+
+&aontimer {
+	status = "okay";
+};