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dts: riscv: starfive: align clint description with Linux

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The CLINT (Core Local Interruptor) description was not aligned with
Linux. For example, there's no "riscv,clint0", but "sifive,clint0". The
peripheral is not described as an interrupt-controller either.

Ref. https://elixir.bootlin.com/linux/v5.18.14/source/arch/riscv/boot/
dts/starfive/jh7100.dtsi#L106

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas 2022-07-28 15:50:32 +02:00 committed by Carles Cufí
parent 6de9fcf315
commit af2f5753d8
3 changed files with 22 additions and 6 deletions
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12
dts/bindings/timer/sifive,clint0.yaml Normal file
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@ -0,0 +1,12 @@
# Copyright (c) 2022 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
description: SiFive RISC-V Core-Local Interruptor.
compatible: "sifive,clint0"
include: base.yaml
properties:
reg:
required: true

8
dts/bindings/timer/starfive,jh7100-clint.yaml Normal file
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@ -0,0 +1,8 @@
# Copyright (c) 2022 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
description: Starfive JH7100 RISC-V Core-Local Interruptor.
compatible: "starfive,jh7100-clint"
include: sifive,clint0.yaml

8
dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi
View file

@ -116,14 +116,10 @@
};
clint: clint@2000000 {
compatible = "riscv,clint0";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "starfive,jh7100-clint", "sifive,clint0";
interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
&cpu1intctrl 3 &cpu1intctrl 7 >;
&cpu1intctrl 3 &cpu1intctrl 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
reg-names = "control";
};
plic: plic@c000000 {